115 lines
4.9 KiB
HTML
115 lines
4.9 KiB
HTML
<HTML>
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<center>
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<A HREF="../tlk-toc.html"> Table of Contents</A>,
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<A href="../tlk.html" target="_top"> Show Frames</A>,
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<A href="../processors/processors.html" target="_top"> No Frames</A>
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</center>
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<hr>
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<META NAME="TtH" CONTENT="1.03">
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<p>
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<H1><A NAME="tth_chAp13">Chapter 13 <br>Processors</H1>
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<img src="../logos/sit3-bw-tran.1.gif"><br>
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<p>
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<A NAME="processors-chapter"></A> <tt><b></tt></b>
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Linux runs on a number of processors; this chapter gives a brief outline
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of each of them.
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<p>
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<H2><A NAME="tth_sEc13.1">13.1 </A> X86</H2>
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<p>
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TBD
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<p>
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<H2><A NAME="tth_sEc13.2">13.2 </A> ARM</H2>
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<p>
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The ARM processor implements a low power, high performance 32 bit RISC architecture.
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It is being widely used in embedded devices such as mobile phones and PDAs (Personal
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Data Assistants).
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It has 31 32 bit registers with 16 visible in any mode.
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Its instructions are simple load and store instructions (load a value from memory,
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perform an operation and store the result back into memory).
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One interesting feature it has is that every instruction is conditional.
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For example, you can test the value of a register and, until you next test for
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the same condition, you can conditionally execute instructions as and when you like.
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Another interesting feature is that you can perform arithmetic and shift operations
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on values as you load them.
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It operates in several modes, including a system mode that can be entered from user mode
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via a SWI (software interrupt).
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<p>
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It is a synthasisable core and ARM (the company) does not itself manufacture
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processors. Instead the ARM partners (companies such as Intel or LSI for
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example) implement the ARM architecture in silicon.
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It allows other processors to be tightly coupled via a co-processor interface and
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it has several memory management unit variations. These range from simple memory
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protection schemes to complex page hierarchies.
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<p>
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<H2><A NAME="tth_sEc13.3">13.3 </A> Alpha AXP Processor</H2>
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<p>
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The Alpha AXP architecture is a 64-bit load/store RISC architecture designed
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with speed in mind.
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All registers are 64 bits in length; 32 integer registers and 32 floating
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point registers. Integer register 31 and floating point register 31 are
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used for null operations. A read from them generates a zero value and
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a write to them has no effect.
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All instructions are 32 bits long and memory operations are either reads
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or writes.
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The architecture allows different implementations so long as the
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implementations follow the architecture.
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<p>
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There are no instructions that operate directly on values stored in
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memory; all data manipulation is done between registers.
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So, if you want to increment a counter in memory, you first read it
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into a register, then modify it and write it out.
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The instructions only interact with each other by one instruction
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writing to a register or memory location and another register reading
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that register or memory location.
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One interesting feature of Alpha AXP is that there are instructions
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that can generate flags, such as testing if two registers are equal,
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the result is not stored in a processor status register, but is instead
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stored in a third register.
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This may seem strange at first, but removing this dependency from
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a status register means that it is much easier to build a CPU which
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can issue multiple instructions every cycle.
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Instructions on unrelated registers do not have to wait for each other
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to execute as they would if there were a single status register.
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The lack of direct operations on memory and the large number of registers
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also help issue multiple instructions.
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<p>
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The Alpha AXP architecture uses a set of subroutines, called privileged
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architecture library code (PALcode).
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PALcode is specific to the operating system, the CPU implementation
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of the Alpha AXP architecture and to the system hardware.
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These subroutines provide operating system primitives for context
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switching, interrupts, exceptions and memory management.
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These subroutines can be invoked by hardware or by CALL_PAL
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instructions.
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PALcode is written in standard Alpha AXP assembler with some
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implementation specific extensions to provide direct access to low
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level hardware functions, for example internal processor registers.
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PALcode is executed in PALmode, a privileged mode that stops some
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system events happening and allows the PALcode complete control of
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the physical system hardware.
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<p>
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<p><hr><small>File translated from T<sub><font size=-1>E</font></sub>X by <a href="http://hutchinson.belmont.ma.us/tth/tth.html">T<sub><font size=-1>T</font></sub>H</a>, version 1.0.</small>
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<hr>
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<center>
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<A HREF="../processors/processors.html"> Top of Chapter</A>,
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<A HREF="../tlk-toc.html"> Table of Contents</A>,
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<A href="../tlk.html" target="_top"> Show Frames</A>,
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<A href="../processors/processors.html" target="_top"> No Frames</A><br>
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<EFBFBD> 1996-1999 David A Rusling <A HREF="../misc/copyright.html">copyright notice</a>.
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</center>
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