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<TITLE>The Linux Cache Flush Architecture</TITLE>
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<LINK rel="owner" href="mailto:">
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<BODY>
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<strong>The
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HyperNews <a href="../khg.html">Linux KHG</a>
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Discussion Pages</strong>
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<hr>
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<h3>1. The Players</h3>
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<dl>
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<dt>The TLB.
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<dd>This is more of a virtual entity than a strict
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model as far as the Linux flush architecture is concerned.
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The only characteristics it has is:
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<ol>
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<li>It keeps track of process/kernel mappings in
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some way, whether in software or hardware.
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<li>Architecture specific code may need to be
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notified when the kernel has changed a
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process/kernel mapping.
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</ol>
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<dt>The cache.
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<dd>This entity is essentially "memory state" as
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the flush architecture views it. In general it has the
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following properties:
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<ol>
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<li>It will always hold copies of data which will
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be viewed as uptodate by the local processor.
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<li>Its proper functioning may be related to the
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TLB and process/kernel page mappings in some
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way, that is to say they may depend upon each
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other.
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<li>It may, in a virtually cached configuration, cause
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aliasing problems if one physical page is mapped
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at the same time to two virtual pages, and due to
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to the bits of an address used to index the cache
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line, the same piece of data can end up residing
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in the cache twice, allowing inconsistancies to
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result.
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<li>Devices and DMA may or may not be able to see the
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most up to date copy of a piece of data which
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resides in the cache of the local processor.
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<li>Currently, it is assumed that coherence in a
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multiprocessor environment is maintained by the
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cache/memory subsystem. That is to say, when
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one processor requests a datum on the memory bus
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and another processor has a more uptodate copy,
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by whatever means the requestor will get the
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uptodate copy owned by the other processor.
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</ol>
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</dl>
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(NOTE: SMP architectures without hardware cache coherence
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mechanisms are indeed possible, the current flush
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architecture does not handle this currently. If at
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at some point a Linux port to some system where this
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is an issue occurrs, I will add the necessary hooks.
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But it will not be pretty.)
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<h3>2. What the flush architecture cares about</h3>
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<ol>
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<li>At all times the memory management hardware's view of
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a set of process/kernel mappings will be consistant
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with that of the kernel page tables.
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<li>If the memory management kernel code makes a modification
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to a user process page, by modifying the data via the
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kernel-space alias of the underlying physical page, the
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user thread of control will see the right data before it is
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allowed to continue execution, regardless of the cache
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architecture and/or semantics.
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<li>In general, when address space state is changed (on the
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generic kernel memory management code's behalf <b>only</b>) the
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appropriate flush architecture hook will be called
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describing that state change in full.
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</ol>
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<h3>3. What the flush architecture does not care about</h3>
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<ol>
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<li>DMA/Driver coherency. This includes DMA mappings
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(in the sense of MMU mappings) and cache/DMA datum
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consistency. These sorts of issues have no buisness
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in the flush architecture, see below how they should
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be handled.
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<li>Split Instruction/Data cache consistancy with respect
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to modifications made to the process instruction space
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performed by the signal dispatch code. Again see below
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on how this should be handled in another way.
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</ol>
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<h3>4. The interfaces for the flush architecture and how to implement them</h3>
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In general all of the routines described below will be
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called with the following sequence:
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<pre>
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flush_cache_foo(...);
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modify_address_space();
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flush_tlb_foo(...);
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</pre>
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The logic here is:
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<ol>
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<li>It may be illegal in a given architecture for
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a piece of cache data to exist when no mapping
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for that data exists, therefore the flush must
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occur before the change is made.
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<li>It is possible for a given MMU/TLB architecture
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to perform a hardware table walk of the kernel
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page tables. Therefore the TLB flush is done
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after the page tables have been changed so that
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afterwards the hardware can only load in the new
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copy of the page table information to the TLB.
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</ol>
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<pre><b>
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void flush_cache_all(void);
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void flush_tlb_all(void);
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</b></pre>
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These routines are to notify the architecture specific code
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that a change has been made to the kernel address space
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mappings, which means that the mappings of every process has
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effectively changed.
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<p>
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An implementation shall:
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<ol>
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<li>Eliminate all cache entries which are valid
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at this point in time when <tt>flush_cache_all</tt>
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is invoked. This applies to virtual cache
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architectures. If the cache is write-back
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in nature, this routine shall commit the cache
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data to memory before invalidating each entry.
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For physical caches, no action need be performed
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since physical mappings have no bearing on
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address space translations.
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<li>For <tt>flush_tlb_all</tt>, all TLB mappings for the kernel
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address space should be made consistant with the
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OS page tables by whatever means necessary. Note
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that with an architecture that possesses the notion
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of "MMU/TLB contexts" it may be necessary to
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perform this synchronization in every "active"
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MMU/TLB context.
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</ol>
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<pre><b>
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void flush_cache_mm(struct mm_struct *mm);
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void flush_tlb_mm(struct mm_struct *mm);
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</b></pre>
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These routines notify the system that the entire address
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space described by the <tt>mm_struct</tt> passed is changing. Please
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take note of two things in particular:
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<ol>
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<li>The <tt>mm_struct</tt> is the unit of mmu/tlb real estate
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as far as the flush architecture is concerned.
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In particular, an <tt>mm_struct</tt> may map to one or
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many tasks or none!
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<li>This "address space" change is considered to be
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occurring in user space only. It is therefore safe
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for code to avoid flushing kernel tlb/cache
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entries if that is possible for efficiency.
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</ol>
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An implementation shall:
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<ol>
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<li>For <tt>flush_cache_mm</tt>, whatever entries could exist
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in a virtual cache for the address space described
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by <tt>mm_struct</tt> are to be invalidated.
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<li>For <tt>flush_tlb_mm</tt>, the tlb/mmu hardware is to be
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placed in a state where it will see the (now
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current) kernel page table entries for the address
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space described by the <tt>mm_struct</tt>.
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</ol>
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<pre><b>
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flush_cache_range(struct mm_struct *mm, unsigned long start,
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unsigned long end);
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flush_tlb_range(struct mm_struct *mm, unsigned long start,
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unsigned long end);
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</pre></b>
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A change to a particular range of user addresses in the
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address space described by the <tt>mm_struct</tt> passed is occurring.
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The two notes above for <tt>flush_*_mm()</tt> concerning the <tt>mm_struct</tt>
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passed apply here as well.
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<p>
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An implementation shall:
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<ol>
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<li>For <tt>flush_cache_range</tt>, on a virtually cached
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system, all cache entries which are valid
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for the range start to end in the address space
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described by the <tt>mm_struct</tt> are to be invalidated.
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<li>For <tt>flush_tlb_range</tt>, whatever actions necessary
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to cause the MMU/TLB hardware to not contain
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stale translations are to be performed. This
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means that whatever translations are in the kernel
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page tables in the range start to end in the
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address space described by the <tt>mm_struct</tt> are to
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be what the memory mangement hardware will see from
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this point forward, by whatever means.
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</ol>
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<pre><b>
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void flush_cache_page(struct vm_area_struct *vma, unsigned long address);
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long address);
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</b></pre>
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A change to a single page at <tt>address</tt> within user space to
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the address space described by the <tt>vm_area_struct</tt> passed is
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occurring. An implementation, if need be, can get at the
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assosciated <tt>mm_struct</tt> for this address space via <tt>vma->vm_mm</tt>.
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The VMA is passed for convenience so that an implementation
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can inspect <tt>vma->vm_flags</tt>. This way in an implementation
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where the instruction and data spaces are not unified, one can
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check to see if <tt>VM_EXEC</tt> is set in <tt>vma->vm_flags</tt> to possibly
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avoid flushing the instruction space, for example.
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<p>
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The two notes above for <tt>flush_*_mm()</tt> concerning the <tt>mm_struct</tt>
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(passed indirectly via <tt>vma->vm_mm</tt>) apply here as well.
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<p>
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An implementation shall:
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<ol>
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<li>For <tt>flush_cache_range</tt>, on a virtually cached
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system, all cache entries which are valid
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for the page at <tt>address</tt> in the address space
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described by the VMA are to be invalidated.
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<li>For <tt>flush_tlb_range</tt>, whatever actions necessary
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to cause the MMU/TLB hardware to not contain
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stale translations are to be performed. This
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means that whatever translations are in the kernel
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page tables for the page at <tt>address</tt> in the
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address space described by the VMA passed are to
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be what the memory mangement hardware will see from
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this point forward, by whatever means.
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</ol>
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<pre><b>
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void flush_page_to_ram(unsigned long page);
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</b></pre>
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This is the ugly duckling. But its semantics are necessary
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on so many architectures that I needed to add it to the flush
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architecture for Linux.
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<p>
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Briefly, when (as one example) the kernel services a COW
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fault, it uses the aliased mappings of all physical memory
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in kernel space to perform the copy of the page in question
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to a new page. This presents a problem for virtually indexed
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caches which are write-back in nature. In this case, the
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kernel touches two physical pages in kernel space. The code
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sequence being described here essentially looks like:
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<pre>
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do_wp_page()
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{
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[ ... ]
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copy_cow_page(old_page,new_page);
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flush_page_to_ram(old_page);
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flush_page_to_ram(new_page);
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flush_cache_page(vma, address);
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modify_address_space();
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free_page(old_page);
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flush_tlb_page(vma, address);
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[ ... ]
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}
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</pre>
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(Some of the actual code has been simplified for example
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purposes.)
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<p>
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Consider a virtually indexed cache which is write-back.
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At the point in time at which the copy of the page occurs
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to the kernel space aliases, it is possible for the user
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space view of the original page to be in the caches (at
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the user's address, ie. where the fault is occurring).
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The page copy can bring this data (for the old page)
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into the caches. It will also place the data (at the new
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kernel aliased mapping of the page) being copied to into
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the cache, and for write back caches this data will be dirty
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or modified in the cache.
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<p>
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In such a case main memory will not see the most recent copy
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of the data. The caches are stupid, so for the new page we
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are giving to the user, without forcing the cached data at the
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kernel alias to main memory the process will see the old
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contents of the page (ie. whatever garbage was there before
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the copy done by COW processing above).
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<p>
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A concrete example of what was just described:
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<p>
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Consider a process which shares a page, read-only with another
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task (or many) at virtual address 0x2000 in user space. And
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for example purposes let us say that this virtual address maps
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to physical page 0x14000.
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<pre>
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Virtual Pages
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task 1 --------------
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| 0x00000000 |
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--------------
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| 0x00001000 | Physical Pages
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-------------- --------------
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| 0x00002000 | --\ | 0x00000000 |
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-------------- \ --------------
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\ | ... |
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task 2 -------------- \ --------------
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| 0x00000000 | |----> | 0x00014000 |
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-------------- / --------------
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| 0x00001000 | / | ... |
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-------------- / --------------
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| 0x00002000 | --/
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--------------
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</pre>
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If task 2 tries to write to the read-only page at address
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0x2000 we will get a fault and eventually end up at the
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code fragment shown above in <tt>do_wp_page()</tt>.
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<p>
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The kernel will get a new page for task2, let us say this
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is physical page 0x26000, and let us also say that the kernel
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alias mappings for physical pages 0x14000 and 0x26000 can
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reside in the two unique cache lines at the same time based
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upon the line indexing scheme of this cache.
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<p>
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The page contents get copied from the kernel mappings for
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physical page 0x14000 to the ones for physical page 0x26000.
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<p>
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At this point in time, on a write-back virtually indexed cache
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architecture we have a potential inconsistancy. The new data
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copied into physical page 0x26000 is not necessary in main
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memory at this point, in fact it could be all in the cache
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only at the kernel alias of the physical address. Also, the
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(non-modified, ie. clean) data for the original (old) page
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is in the cache at the kernel alias for physical page 0x14000,
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this can produce an inconsistancy later on, so to be safe it
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is best to be eliminate the cached copies of this data as
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well.
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<p>
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Let us say we did not write back the data for the page at
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0x26000 and we let it just stay there. We would return
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to task 2 (who has this new page now mapped in at virtual
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address 0x2000), he would complete his write, then he
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would read some other piece of data in this new page (i.e.
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expecting the contents that existed there beforehand).
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At this point in time if the data is left in the cache
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at the kernel alias for the new physical page, the user
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will get whatever was in main memory before the copy
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for his read. This can lead to disasterous results.
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<p>
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Therefore an architecture shall:
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<dl><dd>On virtually indexed cache architectures, do whatever
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is necessary to make main memory consistant with the
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cached copy of the kernel space page passed.
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</dl>
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<p>
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NOTE: It is actually necessary for this routine to invalidate
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lines in a virtual cache which is not write-back in
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nature. To see why this is really necessary, replay
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the above example with task 1 and 2, but this time
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<tt>fork()</tt> yet another task 3 before the COW faults occur,
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consider the contents of the caches in both kernel and
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user space if the following sequence occurrs in exact
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succession:
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<ol>
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<li>task 1 reads some the page at 0x2000
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<li>task 2 COW faults the page at 0x2000
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<li>task 2 performs his writes to the new page at 0x2000
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<li>task 3 COW faults the page at 0x2000
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</ol>
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Even on a non-writeback virtually indexed cache,
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task 3 can see inconsistant data after the COW
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fault if <tt>flush_page_to_ram</tt> does not invalidate the
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kernel aliased physical page from the cache.
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<pre><b>
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void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t pte);
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</b></pre>
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Although not strictly part of the flush architecture, on
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certain architectures some critical operations and checks
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need to be performed here for things to work out properly
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and for the system to remain consistant.
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<p>
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In particular, for virtually indexed caches this routine
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must check to see that the new mapping being added by
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the current page fault does not add an "bad alias" to user
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space.
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<p>
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A "bad alias" is defined as two or more mappings (at least one
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of which is writable) to two or more virtual pages which all
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translate to the same exact physical page, and due to the
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indexing algorithm of the cache can also reside in unique
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and mutually exclusive cache lines.
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<p>
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If such a "bad alias" is detected an implementation needs to
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resolve this inconsistancy some how, one solution is to
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walk through all of the mappings and change the page tables
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to make these pages as "non-cacheable" if the hardware allows
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such a thing.
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<p>
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The checks for this are very simple, all an implementation
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needs to do essentially is:
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<pre>
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if((vma->vm_flags & (VM_WRITE|VM_SHARED)) == (VM_WRITE|VM_SHARED))
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check_for_potential_bad_aliases();
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</pre>
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So for the common case (shared writable mappings are extremely
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rare) only one comparison is needed for systems with virtually
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indexed caches.
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<h3>5. Implications for SMP</h3>
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Depending upon the architecture certain amends may be needed
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to allow the flush architecture to work on an SMP system.
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<p>
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The main concern is whether one of the above flush operations
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cause the entire system to be globally see the flush, or the
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flush is only guarenteed to be seen by the local processor.
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<p>
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In the latter case a cross calling mechanism is needed.
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The current two SMP systems supported under Linux (Intel
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and Sparc) use inter-processor interrupts to "broadcast" the
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flush operation and cause it to run locally on all processors
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if necessary.
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<p>
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As an example, on sun4m Sparc systems all processers in the
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system must execute the flush request to guarentee consistancy
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across the entire system. However, on sun4d Sparc machines,
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TLB flushes performed on the local processor are broadcast
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over the system bus by the hardware and therefore a cross
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call is not necessary.
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<h3>6. Implications for context based MMU/CACHE architectures</h3>
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The entire idea behind the concept of MMU and cache context
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facilities is to allow many address spaces to share the
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cache/mmu resources on the cpu.
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<p>
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To take full advantage of such a facility, and still maintain
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coherency as described above, requires some extra
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consideration from the implementor.
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<p>
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The issues involved will vary greatly from one implementation
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to another, at least this has been the experience of the
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author. But in particular some of the issues are likely
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to be:
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<ol>
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<li>The relationship of kernel space mappings to
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user space ones, as far as contexts are concerned.
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On some systems kernel mappings have a "global"
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attribute, in that the hardware does not concern
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itself with context information when a translation
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is made which has this attribute. Therefore one
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flush (in any context) of a kernel cache/mmu
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mapping could be sufficient.
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<br>
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However it is possible in other implementations
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for the kernel to share the context key assosciated
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with a particular address space. It may be necessary
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in such a case to walk into all contexts which are
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currently valid and perform the complete flush in
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each one for a kernel address space flush.
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<li>The cost of per-context flushes can become a key
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issue, especially with respect to the TLB. For
|
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example, if a tlb flush is needed on a large
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range of addresses (or an entire address space)
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it may be more prudent to allocate and assign a new
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mmu context to this process for the sake of
|
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efficiency.
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</ol>
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<h3>7. How to handle what the flush architecture does not do, with examples</h3>
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|
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The flush architecture just described make no amends for
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|
device/DMA coherency with cached data. It also has no
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|
provisions for any mapping strategies necessary for DMA
|
|
and devices should that be necessary on a certain machine
|
|
Linux is ported to. Such issues are none of the flush
|
|
architectures buisness.
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<p>
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Such issues are most cleanly dealt with at the device driver
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|
level. The author is convinced of this after his experiance
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|
with a common set of Sparc device drivers which needed to
|
|
all function correctly on more than a handfull of cache/mmu
|
|
and bus architecrures in the <b>same</b> kernel.
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|
<p>
|
|
In fact this implementation is more efficient because the
|
|
driver knows exactly when DMA needs to see consistant data
|
|
or when DMA is going to create an inconsistancy which must
|
|
be resolved. Any attempt to reach this level of efficiency
|
|
via hooks added to the generic kernel memory management code
|
|
would be complex and if anything very unclean.
|
|
<p>
|
|
As an example, consider on the Sparc how DMA buffers are
|
|
handled. When a device driver must perform DMA to/from
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|
either a single buffer or a scatter list of many buffers
|
|
it uses a set of abstract routines:
|
|
<pre>
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|
char *(*mmu_get_scsi_one)(char *, unsigned long, struct linux_sbus *sbus);
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|
void (*mmu_get_scsi_sgl)(struct mmu_sglist *, int, struct linux_sbus *sbus);
|
|
void (*mmu_release_scsi_one)(char *, unsigned long, struct linux_sbus *sbus);
|
|
void (*mmu_release_scsi_sgl)(struct mmu_sglist *, int, struct linux_sbus *sbus);
|
|
void (*mmu_map_dma_area)(unsigned long addr, int len);
|
|
</pre>
|
|
Essentially the <tt>mmu_get_*</tt> routines are passed a pointer or
|
|
a set pointers and size specifications to areas in kernel
|
|
space for which DMA will occur, they return a DMA capable
|
|
address (i.e. one which can be loaded into the DMA controller
|
|
for the transfer). When the driver is done with the DMA and
|
|
the transfer has completed the <tt>mmu_release_*</tt> routines must
|
|
be called with the DMA'able address(es) so that the resources
|
|
can be freed (if necessary) and cache flushes can be performed
|
|
(if necessary).
|
|
<p>
|
|
The final routine is there for drivers which need to have
|
|
a block of DMA memory for a long period of time, for example
|
|
a networking driver would use this for a pool transmit and
|
|
receive buffers.
|
|
<p>
|
|
The final argument is a Sparc specific entity which allows the
|
|
machine level code to perform the mapping if DMA mappings
|
|
are setup on a per-BUS basis.
|
|
|
|
<h2>8. Open issues</h2>
|
|
|
|
There seems to be some very stupid cache architectures out
|
|
there which want to cause trouble when an alias is placed
|
|
into the cache (even a safe one where none of the aliased
|
|
cache entries are writable!). Of note is the MIPS R4000
|
|
which will give an exception when such a situation occurs,
|
|
these can occur when COW processing is happing in the
|
|
current implementation. On most chips which do something
|
|
stupid like this, the exception handler can flush the
|
|
entries in the cache being complained about and all is well.
|
|
The author is mostly concerned about the cost of these
|
|
exceptions during COW processing and the effects this will
|
|
have for system performance. Perhaps a new flush is
|
|
neccessary, which would be performed before the page
|
|
copy in COW fault processing, which essentially is to
|
|
flush a user space page if not doing so would cause the
|
|
trouble just described.
|
|
<p>
|
|
There has been heated talk lately about adding page flipping
|
|
facilities for very intelligent networking hardware. It
|
|
may be necessary to extend the flush architecture to provide
|
|
the interfaces and facilities necessary for these changes to
|
|
the networking code.
|
|
<p>
|
|
And by all means, the flush architecture is always subject to
|
|
improvements and changes to handle new issues or new hardware
|
|
which presents a problem that was to this point unknown.
|
|
<p>
|
|
<pre>
|
|
David S. Miller
|
|
davem@caip.rutgers.edu
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</pre>
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