564 lines
22 KiB
Plaintext
564 lines
22 KiB
Plaintext
Brief Introduction to Alpha Systems and Processors
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Neal Crook, Digital Equipment (Editor: David Mosberger
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<mailto:davidm@azstarnet.com>)
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V0.11, 6 June 1997
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This document is a brief overview of existing Alpha CPUs, chipsets and
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systems. It has something of a hardware bias, reflecting my own area
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of expertese. Although I am an employee of Digital Equipment Corpora-
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tion, this is not an official statement by Digital and any opinions
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expressed are mine and not Digital's.
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______________________________________________________________________
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Table of Contents
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1. What is Alpha
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2. What is Digital Semiconductor
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3. Alpha CPUs
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4. 21064 performance vs 21066 performance
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5. A Few Notes On Clocking
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6. The chip-sets
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7. The Systems
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8. Bytes and all that stuff
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9. PALcode and all that stuff
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10. Porting
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11. More Information
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12. References
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______________________________________________________________________
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1. What is Alpha
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"Alpha" is the name given to Digital's 64-bit RISC architecture. The
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Alpha project in Digital began in mid-1989, with the goal of providing
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a high-performance migration path for VAX customers. This was not the
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first RISC architecture to be produced by Digital, but it was the
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first to reach the market. When Digital announced Alpha, in March
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1992, it made the decision to enter the merchant semicondutor market
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by selling Alpha microprocessors.
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Alpha is also sometimes referred to as Alpha AXP, for obscure and
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arcane reasons that aren't worth persuing. Suffice it to say that they
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are one and the same.
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2. What is Digital Semiconductor
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Digital Semiconductor <http://www.digital.com/info/semiconductor/>
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(DS) is the business unit within Digital Equipment Corporation
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(Digital - we don't like the name DEC) that sells semiconductors on
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the merchant market. Digital's products include CPUs, support
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chipsets, PCI-PCI bridges and PCI peripheral chips for comms and
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multimedia.
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3. Alpha CPUs
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There are currently 2 generations of CPU core that implement the Alpha
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architecture:
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o EV4
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o EV5
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Opinions differ as to what "EV" stands for (Editor's note: the true
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answer is of course "Electro Vlassic" ``[1]''), but the number
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represents the first generation of Digital's CMOS technology that the
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core was implemented in. So, the EV4 was originally implemented in
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CMOS4. As time goes by, a CPU tends to get a mid-life performance kick
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by being optically shrunk into the next generation of CMOS process.
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EV45, then, is the EV4 core implemented in CMOS5 process. There is a
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big difference between shrinking a design into a particular technology
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and implementing it from scratch in that technology (but I don't want
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to go into that now). There are a few other wildcards in here: there
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is also a CMOS4S (optical shrink in CMOS4) and a CMOS5L.
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True technophiles will be interested to know that CMOS4 is a 0.75
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micron process, CMOS5 is a 0.5 micron process and CMOS6 is a 0.35
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micron process.
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To map these CPU cores to chips we get:
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21064-150,166
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EV4 (originally), EV4S (now)
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21064-200
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EV4S
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21064A-233,275,300
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EV45
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21066
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LCA4S (EV4 core, with EV4 FPU)
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21066A-233
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LCA45 (EV4 core, but with EV45 FPU)
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21164-233,300,333
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EV5
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21164A-417
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EV56
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21264
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EV6 <http://www.mdronline.com/report/articles/21264/21264.html>
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The EV4 core is a dual-issue (it can issue 2 instructions per CPU
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clock) superpipelined core with integer unit, floating point unit and
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branch prediction. It is fully bypassed and has 64-bit internal data
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paths and tightly coupled 8Kbyte caches, one each for Instruction and
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Data. The caches are write-through (they never get dirty).
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The EV45 core has a couple of tweaks to the EV4 core: it has a
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slightly improved floating point unit, and 16KB caches, one each for
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Instruction and Data (it also has cache parity). (Editor's note: Neal
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Crook indicated in a separate mail that the changes to the floating
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point unit (FPU) improve the performance of the divider. The EV4 FPU
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divider takes 34 cycles for a single-precision divide and 63 cycles
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for a double-precision divide (non data-dependent). In constrast, the
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EV45 divider takes typically 19 cycles (34 cycles max) for single-
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precision and typically 29 cycles (63 cycles max) for a double-
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precision division (data-dependent).)
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The EV5 core is a quad-issue core, also superpipelined, fully bypassed
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etc etc. It has tightly-coupled 8Kbyte caches, one each for I and D.
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These caches are write-through. It also has a tightly-coupled 96Kbyte
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on-chip second-level cache (the Scache) which is 3-way set associative
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and write-back (it can be dirty). The EV4->EV5 performance increase is
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better than just the increase achieved by clock speed improvements. As
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well as the bigger caches and quad issue, there are microarchitectural
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improvements to reduce producer/consumer latencies in some paths.
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The EV56 core is fundamentally the same microarchitecture as the EV5,
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but it adds some new instructions for 8 and 16-bit loads and stores
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(see Section ``Bytes and all that stuff''). These are primarily
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intended for use by device drivers. The EV56 core is implemented in
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CMOS6, which is a 2.0V process.
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The 21064 was anounced in March 1992. It uses the EV4 core, with a
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128-bit bus interface. The bus interface supports the 'easy'
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connection of an external second-level cache, with a block size of
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256-bits (2 data beats on the bus). The Bcache timing is completely
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software configurable. The 21064 can also be configured to use a
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64-bit external bus, (but I'm not sure if any shipping system uses
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this mode). The 21064 does not impose any policy on the Bcache, but it
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is usually configured as a write-back cache. The 21064 does contain
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hooks to allow external hardware to maintain cache coherence with the
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Bcache and internal caches, but this is hairy.
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The 21066 uses the EV4 core and integrates a memory controller and PCI
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host bridge. To save pins, the memory controller has a 64-bit data bus
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(but the internal caches have a block size of 256 bits, just like the
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21064, therefore a block fill takes 4 beats on the bus). The memory
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controller supports an external Bcache and external DRAMs. The timing
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of the Bcache and DRAMs is completely software configurable, and can
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be controlled to the resolution of the CPU clock period. Having a
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4-beat process to fill a cache block isn't as bad as it sounds because
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the DRAM access is done in page mode. Unfortunately, the memory
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controller doesn't support any of the new esoteric DRAMs (SDRAM, EDO
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or BEDO) or synchronous cache RAMs. The PCI bus interface is fully
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rev2.0 compliant and runs at upto 33MHz.
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The 21164 has a 128-bit data bus and supports split reads, with upto 2
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reads outstanding at any time (this allows 100% data bus utilisation
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under best-case dream-on conditions, i.e., you can theoretically
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transfer 128-bits of data on every bus clock). The 21164 supports easy
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connection of an external 3-rd level cache (Bcache) and has all the
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hooks to allow external systems to maintain full cache coherence with
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all caches. Therefore, symmetric multiprocessor designs are 'easy'.
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The 21164A was announced in October, 1995. It uses the EV56 core. It
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is nominally pin-compatible with the 21164, but requires split power
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rails; all of the power pins that were +3.3V power on the 21164 have
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now been split into two groups; one group provided 2.0V power to the
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CPU core, the other group supplies 3.3V to the I/O cells. Unlike older
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implementations, the 21164 pins are not 5V-tolerant. The end result of
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this change is that 21164 systems are, in general, not upgradeable to
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the 21164A (though note that it would be relatively straightforward to
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design a 21164A system that could also accommodate a 21164). The
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21164A also has a couple of new pins to support the new 8 and 16-bit
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loads and stores. It also improves the 21164 support for using
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synchronus SRAMs to implement the external Bcache.
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4. 21064 performance vs 21066 performance
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The 21064 and the 21066 have the same (EV4) CPU core. If the same
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program is run on a 21064 and a 21066, at the same CPU speed, then the
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difference in performance comes only as a result of system
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Bcache/memory bandwidth. Any code thread that has a high hit-rate on
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the internal caches will perform the same. There are 2 big performance
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killers:
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1. Code that is write-intensive. Even though the 21064 and the 21066
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have write buffers to swallow some of the delays, code that is
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write-intensive will be throttled by write bandwidth at the system
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bus. This arises because the on-chip caches are write-through.
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2. Code that wants to treat floats as integers. The Alpha architecture
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does not allow register-register transfers from integer registers
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to floating point registers. Such a conversion has to be done via
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memory (And therefore, because the on-chip caches are write-
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through, via the Bcache). (Editor's note: it seems that both the
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EV4 and EV45 can perform the conversion through the primary data
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cache (Dcache), provided that the memory is cached already. In
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such a case, the store in the conversion sequence will update the
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Dcache and the subsequent load is, under certain circumstances,
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able to read the updated d-cache value, thus avoiding a costly
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roundtrip to the Bcache. In particular, it seems best to execute
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the stq/ldt or stt/ldq instructions back-to-back, which is somewhat
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counter-intuitive.)
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If you make the same comparison between a 21064A and a 21066A, there
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is an additional factor due to the different Icache and Dcache sizes
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between the two chips.
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Now, the 21164 solves both these problems: it achieve much higher
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system bus bandwidths (despite having the same number of signal pins -
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yes, I know it's got about twice as many pins as a 21064, but all
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those extra ones are power and ground! (yes, really!!)) and it has
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write-back caches. The only remaining problem is the answer to the
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question "how much does it cost?"
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5. A Few Notes On Clocking
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All of the current Alpha CPUs use high-speed clocks, because their
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microarchitectures have been designed as so-called short-tick designs.
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None of the sytem busses have to run at horrendous speeds as a result
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though:
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o on the 21066(A), 21064(A), 21164 the off-chip cache (Bcache) timing
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is completely programmable, to the resolution of the CPU clock. For
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example, on a 275MHz CPU, the Bcache read access time can be
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controller with a resolution of 3.6ns
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o on the 21066(A), the DRAM timing is completely programmable, to the
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resolution of the CPU clock (not the PCI clock, the CPU clock).
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o on the 21064(A), 21164(A), the system bus frequency is a sub-
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multiple of the CPU clock frequency. Most of the 21064 motherboards
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use a 33MHz system bus clock.
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o Systems that use the 21066 can run the PCI at any frequency
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relative to the CPU. Generally, the PCI runs at 33MHz.
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o Systems that use the APECs chipset (see Section ``'') always have
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their CPU system bus equal to their PCI bus frequency. This means
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that both busses tends to run at either 25MHz or 33MHz (since these
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are the frequencies that scale up to match the CPU frequencies). On
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APECs systems, the DRAM controller timings are software
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programmable in terms of the CPU system bus frequency
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Aside: someone suggested that they were getting bad performance on a
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21066 because the 21066 memory controller was only running at 33MHz.
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Actually, it's the superfast 21064A systems that have memory
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controllers that 'only' run at 33MHz.
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6. The chip-sets
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DS sells two CPU support chipsets. The 2107x chipset (aka APECS) is a
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21064(A) support chiset. The 2117x chipset (aka ALCOR) is a 21164
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support chipset. There will also be 2117xA chipset (aka ALCOR 2) as a
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21164A support chipset.
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Both chipsets provide memory controllers and PCI host bridges for
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their CPU. APECS provides a 32-bit PCI host bridge, ALCOR provides a
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64-bit PCI host bridge which (in accordance with the requirements of
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the PCI spec) can support both 32-bit and 64-bit PCI devices.
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APECS consists of 6, 208-pin chips (4, 32-bit data slices (DECADE), 1
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system controller (COMANCHE), 1 PCI controller (EPIC)). It provides a
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DRAM controller (128-bit memory bus) and a PCI interface. It also does
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all the work to maintain memory coherence when a PCI device DMAs into
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(or out of) memory.
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ALCOR consists of 5 chips (4, 64-bit data slices (Data Switch, DSW) -
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208-pin PQFP and 1 control (Control, I/O Address, CIA) - a 383 pin
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plastic PGA). It provides a DRAM controller (256-bit memory bus) and
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a PCI interface. It also does all the work required to support an
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external Bcache and to maintain memory coherence when a PCI device
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DMAs into (or out of) memory.
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There is no support chipset for the 21066, since the memory controller
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and PCI host bridge functionality are integrated onto the chip.
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7. The Systems
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The applications engineering group in DS produces example designs
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using the CPUs and support chipsets. These are typically PC-AT size
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motherboards, with all the functionality that you'd typically find on
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a high-end Pentium motherboard. Originally, these example designs were
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intended to be used as starting points for third-parties to produce
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motherboard designs from. These first-generation designs were called
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Evaluation Boards (EBs). As the amount of engineering required to
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build a motherboard has increased (due to higher-speed clocks and the
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need to meet RF emission and susceptibility regulations) the emphasis
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has shifted towards providing motherboards that are suitable for
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volume manufacture.
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Digital's system groups have produced several generations of machines
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using Alpha processors. Some of these systems use support logic that
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is designed by the systems groups, and some use commodity chipsets
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from DS. In some cases, systems use a combination of both.
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Various third-parties build systems using Alpha processors. Some of
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these companies design systems from scratch, and others use DS support
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chipsets, clone/modify DS example designs or simply package systems
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using build and tested boards from DS.
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The EB64: Obsolete design using 21064 with memory controller
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implemented using programmable logic. I/O provided by using
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programmable logic to interface a 486<->ISA bridge chip. On-board
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Ethernet, SuperI/O (2S, 1P, FD), Ethernet and ISA. PC-AT size. Runs
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from standard PC power supply.
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The EB64+: Uses 21064 or 21064A and APECs. Has ISA and PCI expansion
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(3 ISA, 2 PCI, one pair are on a shared slot). Supports 36-bit DRAM
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SIMs. ISA bus generated by Intel SaturnI/O PCI-ISA bridge. On-board
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SCSI (NCR 810 on PCI) Ethernet (Digital 21040), KBD, MOUSE (PS2
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style), SuperI/O (2S, 1P, FD), RTC/NVRAM. Boot ROM is EPROM. PC-AT
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size. Runs from standard PC power supply.
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The EB66: Uses 21066 or 21066A. I/O sub-system is identical to EB64+.
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Baby PC-AT size. Runs from standard PC power supply. The EB66
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schematic was published as a marketing poster advertising the 21066 as
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"the first microprocessor in the world with embedded PCI" (for trivia
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fans: there are actually 2 versions of this poster - I drew the
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circuits and wrote the spiel for the first version, and some Americans
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mauled the spiel for the second version)
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The EB164: Uses 21164 and ALCOR. Has ISA and PCI expansion (3 ISA
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slots, 2 64-bit PCI slots (one is shared with an ISA slot) and 2
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32-bit PCI slots. Uses plus-in Bcache SIMMs. I/O sub-system provides
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SuperI/O (2S, 1P, FD), KBD, MOUSE (PS2 style), RTC/NVRAM. Boot ROM is
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Flash. PC-AT-sized motherboard. Requires power supply with 3.3V
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output.
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The AlphaPC64 (aka Cabriolet): derived from EB64+ but now baby-AT with
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Flash boot ROM, no on-board SCSI or Ethernet. 3 ISA slots, 4 PCI slots
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(one pair are on a shared slot), uses plug-in Bcache SIMMs. Requires
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power supply with 3.3V output.
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The AXPpci33 (aka NoName), is based on the EB66. This design is
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produced by Digital's Technical OEM (TOEM) group. It uses the 21066
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processor running at 166MHz or 233MHz. It is a baby-AT size, and runs
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from a standard PC power supply. It has 5 ISA slots and 3 PCI slots
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(one pair are a shared slot). There are 2 versions, with either PS/2
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or large DIN connectors for the keyboard.
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Other 21066-based motherboards: most if not all other 21066-based
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motherboards on the market are also based on EB66 - there's really not
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many system options when designing a 21066 system, because all the
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control is done on-chip.
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Multia (aka the Universal Desktop Box): This is a very compact
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pedestal desktop system based on the 21066. It includes 2 PCMCIA
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sockets, 21030 (TGA) graphics, 21040 Ethernet and NCR 810 SCSI disk
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along with floppy, 2 serial ports and a parallel port. It has limited
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expansion capability (one PCI slot) due to its compact size. (There is
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some restriction on when you can use the PCI slot, can't remember
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what) (Note that 21066A-based and Pentium-based Multia's are also
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available).
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DEC PC 150 AXP (aka Jensen): This is a very old Digital system - one
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of the first-generation Alpha systems. It is only mentioned here
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because a number of these systems seem to be available on the second-
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hand market. The Jensen is a floor-standing tower system which used a
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150MHz 21064 (later versions used faster CPUs but I'm not sure what
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speeds). It used programmable logic to interface a 486 EISA I/O bridge
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to the CPU.
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Other 21064(A) systems: There are 3 or 4 motherboard designs around
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(I'm not including Digital systems here) and all the ones I know of
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are derived from the EB64+ design. These include:
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o EB64+ (some vendors package the board and sell it unmodified); AT
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form-factor.
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o Aspen Systems motherboard: EB64+ derivative; baby-AT form-factor.
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o Aspen Systems server board: many PCI slots (includes PCI bridge).
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o AlphaPC64 (aka Cabriolet), baby AT form-factor.
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Other 21164(A) systems: The only one I'm aware of that isn't simply an
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EB164 clone is a system made by DeskStation. That system is
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implemented using a memory and I/O controller proprietary to Desk
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Station. I don't know what their attitude towards Linux is.
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8. Bytes and all that stuff
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When the Alpha architecture was introduced, it was unique amongst RISC
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architectures for eschewing 8-bit and 16-bit loads and stores. It
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supported 32-bit and 64-bit loads and stores (longword and quadword,
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in Digital's nomenclature). The co-architects (Dick Sites, Rich Witek)
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justified this decision by citing the advantages:
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1. Byte support in the cache and memory sub-system tends to slow down
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accesses for 32-bit and 64-bit quantities.
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2. Byte support makes it hard to build high-speed error-correction
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circuitry into the cache/memory sub-system.
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Alpha compensates by providing powerful instructions for manipulating
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bytes and byte groups within 64-bit registers. Standard benchmarks for
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string operations (e.g., some of the Byte benchmarks) show that Alpha
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performs very well on byte manipulation.
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The absence of byte loads and stores impacts some software semaphores
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and impacts the design of I/O sub-systems. Digital's solution to the
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I/O problem is to use some low-order address lines to specify the data
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size during I/O transfers, and to decode these as byte enables. This
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so-called Sparse Addressing wastes address space and has the
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consequence that I/O space is non-contiguous (more on the intricacies
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of Sparse Addressing when I get around to writing it). Note that I/O
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space, in this context, refers to all system resources present on the
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PCI and therefore includes both PCI memory space and PCI I/O space.
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With the 21164A introduction, the Alpha archtecture was ECO'd to
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include byte addressing. Executing these new instructions on an
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earlier CPU will cause an OPCDEC PALcode exception, so that the
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PALcode will handle the access. This will have a performance impact.
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The ramifications of this are that use of these new instructions (IMO)
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should be restricted to device drivers rather than applications code.
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These new byte load and stores mean that future support chipsets will
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be able to support contiguous I/O space.
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9. PALcode and all that stuff
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This is a placeholder for a section explaining PALcode. I will write
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it if there is sufficient interest.
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10. Porting
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|
The ability of any Alpha-based machine to run Linux is really only
|
|
limited by your ability to get information on the gory details of its
|
|
innards. Since there are Linux ports for the E66, EB64+ and EB164
|
|
boards, all systems based on the 21066, 21064/APECS or 21164/ALCOR
|
|
should run Linux with little or no modification. The major thing that
|
|
is different between any of these motherboards is the way that they
|
|
route interrupts. There are three sources of interrupts:
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|
o on-board devices
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|
o PCI devices
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|
o ISA devices
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|
All the systems use an Intel System I/O bridge (SIO) to act as a
|
|
bridge between PCI and ISA (the main I/O bus is PCI, the ISA bus is a
|
|
secondary bus used to support slow-speed and 'legacy' I/O devices).
|
|
The SIO contains the traditional pair of daisy-chained 8259s.
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Some systems (e.g., the Noname) route all of their interrupts through
|
|
the SIO and thence to the CPU. Some systems have a separate interrupt
|
|
controller and route all PCI interrupts plus the SIO interrupt (8259
|
|
output) through that, and all ISA interrupts through the SIO.
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Other differences between the systems include:
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|
o how many slots they have
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|
o what on-board PCI devices they have
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|
o whether they have Flash or EPROM
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11. More Information
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|
|
All of the DS evaluation boards and motherboard designs are license-
|
|
free and the whole documentation kit for a design costs about \$50.
|
|
That includes all the schematics, programmable parts sources, data
|
|
sheets for CPU and support chipset. The doc kits are available from
|
|
Digital Semiconductor distributors. I'm not suggesting that many
|
|
people will want to rush out and buy this, but I do want to point out
|
|
that the information is available.
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Hope that was helpful. Comments/updates/suggestions for expansion to
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|
Neal Crook <mailto:neal.crook@reo.mts.digital.com>.
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12. References
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|
|
[1]
|
|
<http://www.research.digital.com/wrl/publications/abstracts/TN-13.html>
|
|
Bill Hamburgen, Jeff Mogul, Brian Reid, Alan Eustace, Richard Swan,
|
|
Mary Jo Doherty, and Joel Bartlett. Characterization of Organic
|
|
Illumination Systems. DEC WRL, Technical Note 13, April 1989.
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