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<TITLE>SPARC-HOWTO.: SPARC, which one ?</TITLE>
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<HR>
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<H2><A NAME="s2">2. SPARC, which one ?</A></H2>
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<P>This document deals only with SPARC based
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computers, in order to check, just
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type <CODE>uname -m</CODE> command and you should read
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something like <CODE>sparc4x</CODE> where x is blank,c,d,m,u
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if the system runs Solaris, or <CODE>sparc</CODE> for 32 bits SPARC architectures
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and <CODE>sparc64</CODE> for 64 bits SPARC architectures if it runs Linux.
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2.x.y
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<P>
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<P>
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<P>SPARC stands for Scalable Processor ARChitecture,
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it derives from research done between 1984-1988
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on the RISC architecture at UC Berkeley.
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It exists 3 versions of this archiecture, SPARC-V7, SPARC-V8
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(32 bits) and SPARC-V9 (64 bits).
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As you are likely to encounter a lot of implementations of
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the SPARC architecture, in the next section, the main features
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of theses processors are summarized.
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<P>
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<H2><A NAME="ss2.1">2.1 Sun SPARC</A>
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</H2>
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<P>This is quite obsolete, it is an implementation of the
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SPARC-V7 ; its main feature are an Integer unit (IU), an external Floating Point Unit (FPU),
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an unified data + instruction 64KB direct associative cache, and an Memory Managment Unit (MMU).
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There is a 4 stage pipeline for the integer instructions
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(fetch F, decode D, exec E, update WB)
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FPU and IU are synchronized.
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<P>
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<H2><A NAME="ss2.2">2.2 Super SPARC</A>
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</H2>
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<P>This is Texas Instrument and Sun's brainchild, it is usualy found at around 50Mhz clok rates
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featuring up to 1MB of L2 cache, it is available both as single and dual processor modules
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(SparcStation 10 and SparcStation 20). The higher clock frequency I
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have encountered so far is 60Mhz.
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<P>On a technical point of view this is a SPARC-V8 implementation,
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it is a superscalar processor,
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having 2 caches, one for instruction the other one for data.
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<UL>
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<LI>The 20kB instruction cache is a 5 way associative.</LI>
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<LI>The 16KB data cache is 4 way associative. </LI>
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</UL>
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<P>
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<H2><A NAME="ss2.3">2.3 Micro SPARC</A>
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</H2>
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<P>This is once again Texas Instrument and Sun's brainchild, it can be found
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in the SparcStation Classic, SparcStation LX, at frequency up to
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50Mhz. Its derivative, the Micro SPARC II can be found in the SparcStation
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4 and SparcStation 5 at frequencies up to 110Mhz.
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<P>On a technical point of view, its main features are a high level of
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integration, having 2 caches, one for instructions, the other one for
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data.
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<P>
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<UL>
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<LI>A 4KB instruction direct associative cache.</LI>
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<LI>A 2KB data direct associative cache.</LI>
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</UL>
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<P>It is not possible to add an L2 cache.
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If you wish to learn more about the MicroSPARC processor you can browse
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Sun's
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<A HREF="http://www.sun.com/processors/index.html"> Ultra SPARC</A> ressources.
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<P>
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<H2><A NAME="ss2.4">2.4 Hyper SPARC</A>
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</H2>
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<P>This processor was introduced by ROSS in 1993, it is usualy found in the
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SparcStation 10, and SparcStation 20, at frequencies up to 150Mhz
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(I have heard of 200Mhz dual processor modules, but Have not
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witnessed one yet). It can be found on single or dual
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processor modules.
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<P>
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On a technical point of view it is an implementation of the SPARC-V8,
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it is superscalar. It can be found with L2 cache up to 512KB
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<P>
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<H2><A NAME="ss2.5">2.5 ERC32</A>
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</H2>
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<P>This is a radhard SPARC V7 microprocessor designed to be used on the
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space segment.
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<P>It comes as a single unit or as a three chip
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package. Main manufacturer is <CODE>ATMEL</CODE> in Nantes,
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France. At least, one software vendor claims to have GNU/Linux running
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on this CPU, this is for the
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<P>
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<A HREF="http://dse.cyberclwn.com/sparc-rtems-erc32.htm">http://dse.cyberclwn.com/sparc-rtems-erc32.htm</A>. This project
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has not been updated since March 2001. As I have not had the
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opportunity to check this claim. I am more than doubtful.
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<P>
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<H2><A NAME="ss2.6">2.6 LEON</A>
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</H2>
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<P>This is also a radhard implementation of the SPARC V8 designed to be
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used on the space segment. It is the ESA's brainchild and the lead
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designer is jiri gaisler.
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More information can be found on LEON's website:
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<A HREF="http://www.gaisler.com/leonmain.html">http://www.gaisler.com/leonmain.html</A><P>The 2.4 and 2.5 kernel series are not yet supported, however the 2.0 kernel
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series is supported by the <CODE>uClinux</CODE> MMU less
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GNU/Linux distribution.
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This distribution has been built at ESA/ESTEC December 26 2003
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on a SuSE 8.0 GNU/Linux distribution
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with gcc version 2.95.3 20010315 and a 2.4.18 kernel.
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Hereafter is the boot sequence and a sample session inside the
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tsim-leon simulator.
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<HR>
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<PRE>
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piou@linux:~/uClinux-dist/images> ./tsim-leon -nfp image.elf
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TSIM/LEON SPARC simulator, version 1.1.4a (evaluation version)
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Copyright (C) 2001, Gaisler Research - all rights reserved.
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This software may only be used with a valid license.
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For latest updates, go to http://www.gaisler.com/
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Comments or bug-reports to tsim@gaisler.com
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FPU disabled
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serial port A on stdin/stdout
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allocated 4096 K RAM memory, in 1 bank(s)
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allocated 2048 K ROM memory
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icache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
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dcache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
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section: .text at 0x0, size 252944 bytes
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section: .data at 0x40000000, size 38452 bytes
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section: .romfs at 0x3dc10, size 67584 bytes
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tsim> g
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resuming at 0x00000000
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aCDG512k RAM
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Found my key
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Moved .data
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Found my key
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uClinux/Sparc
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Flat model support (C) 1998-2000 Kenneth Albanowski, D. Jeff Dionne
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LEON-2.1 Sparc V8 support (C) 2000 D. Jeff Dionne, Lineo Inc.
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LEON-2.2/LEON-2.3 Sparc V8 support (C) 2001 The LEOX team <team@leox.org>.
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Calibrating delay loop.. ok - 6.68 BogoMIPS
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Memory available: 3904k/4080k RAM, 0k/0k ROM (176k kernel data, 247k code)
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Swansea University Computer Society NET3.035 for Linux 2.0
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NET3: Unix domain sockets 0.13 for Linux NET3.035.
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uClinux version 2.0.39.uc2 (root@linux) (gcc version 2.95.3 20010315 (release)) 6 Thu Dec 26 18:28:01 PST 2002
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LEON serial driver version 0.9
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ttyS0 (irq = 3) is a builtin LEON UART
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Blkmem copyright 1998,1999 D. Jeff Dionne
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Blkmem copyright 1998 Kenneth Albanowski
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Blkmem 1 disk images:
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0: 3DC10-4E40F (RO)
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VFS: Mounted root (romfs filesystem) readonly.
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Sash command shell (version 1.1.1)
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/> pwd
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/
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/> cd bin
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/bin> pwd
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/bin
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/bin> ls
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sh
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/bin>
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</PRE>
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<HR>
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<H2><A NAME="ss2.7">2.7 Ultra SPARC</A>
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</H2>
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<P>The Ultra SPARC processor is an extension of the SPARC-V9
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architecture, it is a 64 bits processor, it features some video
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processing instructions. It is found in all the computer whose name
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start with Ultra.
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<P>The Ultra SPARC II is an improvement of the Ultra SPARC, the
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Ultra SPARCIII is actually the second generation of Ultra SPARC
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processors, it was first introduced in the SunBlade 1000 Workstation.
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If wish to learn more about the UltraSPARC processors you can browse
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Sun's
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<A HREF="http://www.sun.com/processors/index.html"> Ultra SPARC</A> ressources.
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<P>
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<H2><A NAME="ss2.8">2.8 SPARC64 V</A>
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</H2>
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<P>
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<P>This processor is based on the SPARC V9 and is made by Fujitsu
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It is a 64bits CPU with some very interesting error handling features such as
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ECC memory for
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the L1 cache, hardware instruction retry, error classification.
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<P>There is a 64 bit virtual address space and 43 bit physical address space.
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It is used in the PRIMEPOWER high end servers to mainframe class of Fujitsu's
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offering.
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<P>The cache is organized as :
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<UL>
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<LI>A 128kB 2 way associative L1 instruction cache</LI>
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<LI>A 128kB 2 way associative L1 data cache</LI>
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<LI>A 2MB unified 4 way associative L2 cache</LI>
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</UL>
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<P>More information can be found on the
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<A HREF="http://www.fujitsu.com/downloads/PRMPWR/JPS1-R1.0-SPARC64V-pub.pdf">http://www.fujitsu.com/downloads/PRMPWR/JPS1-R1.0-SPARC64V-pub.pdf</A>
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whitepaper.
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<P>You may read the
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<A HREF="http://tldp.org/HOWTO/CPU-Design-HOWTO.html">CPU-Design-HOWTO</A>, this HOWTO has a lot of interesting links
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when it comes to studying the CPUs.
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<P>To summarize, the 32 bits workstations are the:
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<UL>
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<LI>The sun4 workstation is the
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sun4/330 model.</LI>
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<LI>The sun4c workstations are the
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SparcStation 1,2, IPC and IPX models.</LI>
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<LI>The sun4m workstations are the
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SparcStation 5, 10 and 20. </LI>
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</UL>
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Only the SparcStation 10 and SparcStation 20 are SMP
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capable: up to 2 CPU modules.
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<P>For more information on the SparcStation 5, 10, 20
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you can read Sun's
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<A HREF="http://docs.sun.com/"> documentation </A>online or download it available.
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<P>The following model have an 64 bits UltraSPARC
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architecture (sun4u).
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SunUltra 1, 2, 5, 10, 30, 60, 80 and SunBlade 1000, 1500, 2000.
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The SunUltra 2, 60, 80 and SunBlade 1000 are SMP capable,
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with the Ultra 80 and SunBlade 1000 and 2000 accepting up to 4 CPU modules,
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the SunUltra 2 and 60 accepting only 2 CPU modules.
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<P>The SunBlade 2000 is the latest one featuring Sun's latest marvel
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the Ultra III CPU, at a premium price of course.
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You can have a summary of the UltraWorkstation still in production
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at
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<A HREF="http://www.sun.com/desktop/products/">Sun's</A> website.
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<P>A lot of information has been compiled in
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the
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<A HREF="http://www.lysator.liu.se/local/datorhandbok/SunHardwareFAQ.html">Sun hardware reference</A> that is found on many sites,
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or on
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<A HREF="http://www.sunhelp.org/info-ref.php">SunHelp</A> 's website.
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<P>
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<H2><A NAME="ss2.9">2.9 Deciphering the CPUs</A>
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</H2>
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<P>At first, a reference like SM61 or RT-200-D-125/512 seems
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to be, to say the least, quite cryptic.
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Actually, understanding theses references is really easy.
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<P>
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<H3>Ross Technology.</H3>
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<P>Theses CPUs's naming scheme is <CODE>RT-a00-b-freq/cache</CODE>
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where
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<UL>
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<LI><CODE>a</CODE> is a digit:
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<UL>
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<LI><CODE>1</CODE> SparcStation 10.</LI>
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<LI><CODE>2</CODE> SparcStation 20.</LI>
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<LI><CODE>6</CODE> SPARC MP600 ( not exactly a workstation ).</LI>
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</UL>
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</LI>
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<LI><CODE>b</CODE> is a letter:
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<UL>
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<LI><CODE>D</CODE> Dual CPU.</LI>
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<LI><CODE>Q</CODE> Quad CPU.</LI>
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<LI><CODE>S</CODE> Single CPU.</LI>
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</UL>
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</LI>
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<LI><CODE>freq</CODE> The frequency expressed in Megahertz.</LI>
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<LI><CODE>cache</CODE> The amount of cache memory expressed in Kilobytes.</LI>
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</UL>
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<P>When these modules are in a workstation the naming convention is
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HSxy, for example <CODE>ywing</CODE> is a SparcStation 20 HS22,
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thus it is easier to have a look inside the workstation.
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<H3>SM modules.</H3>
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<P>This table is extracted from the
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<A HREF="http://faqaboss.sunhelp.org/">FAQABOSS</A>
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<HR>
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<PRE>
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Name Speed( MHz ) Cache( MB ) Number of SuperSparc
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Processors Series
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SM20 33 0 1 I
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SM30 36 0 1 I
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SM40 40 0 1 I
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SM41 40 1 1 I
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SM50 50 0 1 I
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SM51 50 1 1 I
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SM512 50 1 2 I
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SM51-2 50 2 1 I
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SM61 60 1 1 I
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SM61-2 60 2 1 I
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SM71 75 1 1 II
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SM71-2 75 2 1 II
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SM81 85 1 1 II
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SM81-5 85 2 1 II
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</PRE>
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<HR>
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<P>Warning: the <CODE>SM100</CODE> is a <CODE>RT-600-D-40</CODE>
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<P>
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<P>
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<H3>Cypress.</H3>
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<P>Cypress manufactured SPARC compliants processors;
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AFAIK their naming scheme is CYnnn.
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<P>As you can see, this is easy to understand.
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<P>
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<H2><A NAME="ss2.10">2.10 The javastation.</A>
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</H2>
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<P>This is a family of Network computers that used to be manufactured by Sun,
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there is a very good
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<A HREF="http://tldp.org/HOWTO/JavaStation-HOWTO/">JavaStation-HOWTO</A> about it.
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<P>
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<HR>
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