63 lines
2.7 KiB
HTML
63 lines
2.7 KiB
HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
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<HTML>
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<META NAME="GENERATOR" CONTENT="SGML-Tools 1.0.9">
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<TITLE>Brief Introduction to Alpha Systems and Processors: Bytes and all that stuff</TITLE>
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<LINK HREF="Alpha-HOWTO-9.html" REL=next>
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<LINK HREF="Alpha-HOWTO-7.html" REL=previous>
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<LINK HREF="Alpha-HOWTO.html#toc8" REL=contents>
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<A HREF="Alpha-HOWTO-9.html">Next</A>
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<A HREF="Alpha-HOWTO.html#toc8">Contents</A>
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<HR>
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<H2><A NAME="byte ld/st"></A> <A NAME="s8">8. Bytes and all that stuff</A></H2>
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<P> When the Alpha architecture was introduced, it was unique amongst RISC
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architectures for eschewing 8-bit and 16-bit loads and stores. It supported
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32-bit and 64-bit loads and stores (longword and quadword, in Digital's
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nomenclature). The co-architects (Dick Sites, Rich Witek) justified this
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decision by citing the advantages:
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<P>
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<OL>
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<LI> Byte support in the cache and memory
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sub-system tends to slow down accesses for 32-bit and 64-bit quantities.</LI>
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<LI> Byte support makes it hard to build high-speed error-correction
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circuitry into the cache/memory sub-system.
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</LI>
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</OL>
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<P>
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<P> Alpha compensates by providing powerful instructions for
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manipulating bytes and byte groups within 64-bit registers. Standard
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benchmarks for string operations (e.g., some of the Byte benchmarks) show
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that Alpha performs very well on byte manipulation.
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<P>
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<P> The absence of byte loads and stores impacts some software semaphores and
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impacts the design of I/O sub-systems. Digital's solution to the I/O problem is
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to use some low-order address lines to specify the data size during I/O
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transfers, and to decode these as byte enables. This so-called Sparse
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Addressing wastes address space and has the consequence that I/O space is
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non-contiguous (more on the intricacies of Sparse Addressing when I get around
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to writing it). Note that I/O space, in this context, refers to all system
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resources present on the PCI and therefore includes both PCI memory space and
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PCI I/O space.
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<P>
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<P> With the 21164A introduction, the Alpha archtecture was ECO'd to include
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byte addressing. Executing these new instructions on an earlier CPU will cause
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an OPCDEC PALcode exception, so that the PALcode will handle the access. This
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will have a performance impact. The ramifications of this are that use of these
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new instructions (IMO) should be restricted to device drivers rather than
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applications code.
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<P>
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<P> These new byte load and stores mean that future support chipsets will be
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able to support contiguous I/O space.
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<P>
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<P>
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<HR>
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<A HREF="Alpha-HOWTO-9.html">Next</A>
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<A HREF="Alpha-HOWTO.html#toc8">Contents</A>
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</BODY>
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</HTML>
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