59 lines
2.3 KiB
HTML
59 lines
2.3 KiB
HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
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<TITLE>Brief Introduction to Alpha Systems and Processors: A Few Notes On Clocking</TITLE>
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<LINK HREF="Alpha-HOWTO-6.html" REL=next>
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<HR>
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<H2><A NAME="s5">5. A Few Notes On Clocking</A></H2>
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<P> All of the current Alpha CPUs use high-speed clocks, because their
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microarchitectures have been designed as so-called short-tick
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designs. None of the sytem busses have to run at horrendous speeds as
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a result though:
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<P>
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<UL>
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<LI> on the 21066(A), 21064(A), 21164 the off-chip cache (Bcache)
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timing is completely programmable, to the resolution of the CPU
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clock. For example, on a 275MHz CPU, the Bcache read access time can
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be controller with a resolution of 3.6ns
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</LI>
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<LI> on the 21066(A), the DRAM timing is completely programmable, to
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the resolution of the CPU clock (<EM>not</EM> the PCI clock, the CPU clock).
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</LI>
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<LI> on the 21064(A), 21164(A), the system bus frequency is a
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sub-multiple of the CPU clock frequency. Most of the 21064
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motherboards use a 33MHz system bus clock.
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</LI>
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<LI> Systems that use the 21066 can run the PCI at any frequency
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relative to the CPU. Generally, the PCI runs at 33MHz.
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</LI>
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<LI> Systems that use the APECs chipset (see Section
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<A HREF="Alpha-HOWTO-6.html#The chip-sets">The chip-sets</A>
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) always have their CPU system bus equal to their PCI bus
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frequency. This means that both busses tends to run at either 25MHz or
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33MHz (since these are the frequencies that scale up to match the CPU
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frequencies). On APECs systems, the DRAM controller timings are
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software programmable in terms of the CPU system bus frequency
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</LI>
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</UL>
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<P><B>Aside:</B> someone suggested that they were getting bad performance
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on a 21066 because the 21066 memory controller was only running at
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33MHz. Actually, it's the superfast 21064A systems that have memory
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controllers that 'only' run at 33MHz.
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<P>
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<P>
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