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getauxval.3: Add new cache geometry entries 

Add entries for the new cache geometry values of the auxiliary
vector that got included in the kernel.

Signed-off-by: Raphael Moreira Zinsly <rzinsly@linux.vnet.ibm.com>
Signed-off-by: Michael Kerrisk <mtk.manpages@gmail.com>
This commit is contained in:
Raphael Moreira Zinsly 2019-09-24 10:11:42 -03:00 committed by Michael Kerrisk
parent f3fdbe2812
commit a81869d0e6
1 changed files with 28 additions and 0 deletions
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man3/getauxval.3
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@ -123,6 +123,34 @@ The instruction cache block size.
.\" .TP
.\" .BR AT_NOTELF
.TP
.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147
.BR AT_L1D_CACHEGEOMETRY
Geometry of the L1 data cache, encoded with the cache line size in
bytes in the bottom 16 bits and the cache associativity in the next 16
bits. The associativity is such that if N is the 16-bit value, the cache
is N-way set associative.
.TP
.BR AT_L1D_CACHESIZE
The L1 data cache size.
.TP
.BR AT_L1I_CACHEGEOMETRY
Geometry of the L1 instruction cache, encoded as for AT_L1D_CACHEGEOMETRY.
.TP
.BR AT_L1I_CACHESIZE
The L1 instruction cache size.
.TP
.BR AT_L2_CACHEGEOMETRY
Geometry of the L2 cache, encoded as for AT_L1D_CACHEGEOMETRY.
.TP
.BR AT_L2_CACHESIZE
The L2 cache size.
.TP
.BR AT_L3_CACHEGEOMETRY
Geometry of the L3 cache, encoded as for AT_L1D_CACHEGEOMETRY.
.TP
.BR AT_L3_CACHESIZE
The L3 cache size.
.TP
.BR AT_PAGESZ
The system page size (the same value returned by
.IR sysconf(_SC_PAGESIZE) ).