mirror of https://github.com/mkerrisk/man-pages
prctl.2: Document PR_SET_FP_MODE and PR_GET_FP_MODE
Based on description provided in commit 9791554b and information in https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
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man2/prctl.2
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man2/prctl.2
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@ -263,6 +263,98 @@ or
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Return the endian-ness of the calling process,
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Return the endian-ness of the calling process,
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in the location pointed to by
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in the location pointed to by
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.IR "(int\ *) arg2" .
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.IR "(int\ *) arg2" .
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.\" 9791554b45a2acc28247f66a5fd5bbc212a6b8c8
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.TP
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.BR PR_SET_FP_MODE " (since Linux 4.0, only on MIPS)"
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On MIPS, user land code can be built using ABI which permits linking with a code
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with a more restrictive floating point requirements. For example, user land
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code may be built to target the O32 FPXX ABI and linked with code built for
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either one of the more restrictive FP32 or FP64. When more restrictive code is
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linked in, the overall requirement for the process is to use this more
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restrictive floating point mode. Since kernel has no means of knowing in advance
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which mode process should be executed in, and having possibility that these
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restrictions can be changed during the process' lifetime, the ability to control
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it from the user space via this option is provided.
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.\" https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
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The
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.I (unsigned int) arg2
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argument is a bit mask describing floating point mode used:
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.RS
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.TP
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.BR PR_FP_MODE_FR " = " "(1 << 0)"
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When this bit is
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.I unset
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(so called
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.BR FR=0 " or " FR0
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mode), 32 FP registers are 32-bit wide, and 64-bit registers are represented as
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pair of registers (even- and odd- numbered, with even-numbered register
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containing lower 32 bits, and odd-numbered register containing higher 32 bits).
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When this bit is
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.I set
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(on supported hardware), 32 FP registers are 64-bit wide (so called
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.BR FR=1 " or " FR1
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mode). Note that modern MIPS implementations (MIPS R6 and newer) support
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.B FR=1
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mode only.
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Applications that use O32 FP32 ABI can operate only when this bit is
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.I unset
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.RB ( FR=0 ;
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or they can be used with FRE enabled, see below).
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Applications that use O32 FP64 ABI (and O32 FP64A ABI, which exists for
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providing ability to operate with existing FP32 code; see below) can operate
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only when this bit is
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.I set
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.RB ( FR=1 ).
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Applications that use O32 FPXX ABI can operate in both cases.
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.TP
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.BR PR_FP_MODE_FRE " = " "(1 << 1)"
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Compatibility with 32-bit FP mode. When this mode is enabled, it emulates 32-bit
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FP operations by raising reserved instruction exception on every instruction
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that uses 32-bit formats and kernel then handles the instruction in software
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(the problem lies in discrepancy of handling odd-numbered registers which are
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high 32 bits of 64-bit registers with even numbers in
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.B FR=0
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mode and lower 32-bit parts of odd-numbered 64-bit registers in
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.B FR=1
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mode). Enabling of this bit is needed when code with O32 FP32 ABI should operate
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with code with compatible O32 FPXX or O32 FP64A ABIs (which require
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.B FR=1
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FPU mode) or when it is executed on newer hardware (MIPS R6 onwards) which lacks
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.B FR=0
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mode support when binary with FP32 ABI is used.
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.IP
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Note that this mode only makes sense when FPU is in 64-bit mode
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.RB ( FR=1 .)
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.IP
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Note that usage of emulation inherently has a significant performance hit and
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should be avoided if possible.
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.RE
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.IP
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Note that for N32/N64 ABI is a different story and does not need FPU emulation
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and always operates in
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.B FR=1
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mode.
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.IP
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This option is mainly intended for use by dynamic loader, but may be of use by
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applications in case library loading during runtime (via
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.BR dlopen (3),
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for example) is used.
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.IP
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Arguments
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.IR arg3 ", " arg4 " and " arg5
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are ignored.
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.TP
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.BR PR_GET_FP_MODE " (since Linux 4.0, only on MIPS)"
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Get current floating point mode (see description for
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.B PR_SET_FP_MODE
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for details).
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Call returns bit mask which represents current FP mode in case of success.
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Arguments
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.IR arg2 ", " arg3 ", " arg4 " and " arg5
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are ignored.
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.TP
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.TP
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.BR PR_SET_FPEMU " (since Linux 2.4.18, 2.5.9, only on ia64)"
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.BR PR_SET_FPEMU " (since Linux 2.4.18, 2.5.9, only on ia64)"
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Set floating-point emulation control bits to \fIarg2\fP.
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Set floating-point emulation control bits to \fIarg2\fP.
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@ -1285,6 +1377,14 @@ or
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and the kernel or the CPU does not support MPX management.
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and the kernel or the CPU does not support MPX management.
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Check that the kernel and processor have MPX support.
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Check that the kernel and processor have MPX support.
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.TP
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.TP
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.B EOPNOTSUPP
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.I option
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is
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.B PR_SET_FP_MODE
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and
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.I arg2
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has invalid or unsupported value.
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.TP
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.B EPERM
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.B EPERM
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.I option
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.I option
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is
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is
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