perf_event_open.2: Minor formatting fixes

Signed-off-by: Michael Kerrisk <mtk.manpages@gmail.com>

man2/perf_event_open.2

@@ -379,12 +379,12 @@ to one of the following:
 .TP
 .B PERF_COUNT_HW_CPU_CYCLES
 Total cycles.
-Be wary of what happens during CPU frequency scaling
+Be wary of what happens during CPU frequency scaling.
 .TP
 .B PERF_COUNT_HW_INSTRUCTIONS
 Retired instructions.
 Be careful, these can be affected by various
-issues, most notably hardware interrupt counts
+issues, most notably hardware interrupt counts.
 .TP
 .B PERF_COUNT_HW_CACHE_REFERENCES
 Cache accesses.
@@ -836,15 +836,15 @@ The values of this are the following:
 .TP
 0 -
 .B SAMPLE_IP
-can have arbitrary skid
+can have arbitrary skid.
 .TP
 1 -
 .B SAMPLE_IP
-must have constant skid
+must have constant skid.
 .TP
 2 -
 .B SAMPLE_IP
-requested to have 0 skid
+requested to have 0 skid.
 .TP
 3 -
 .B SAMPLE_IP
@@ -905,19 +905,19 @@ It is one of:
 .RS
 .TP
 .BR HW_BREAKPOINT_EMPTY
-no breakpoint
+No breakpoint.
 .TP
 .BR HW_BREAKPOINT_R
-count when we read the memory location
+Count when we read the memory location.
 .TP
 .BR HW_BREAKPOINT_W
-count when we write the memory location
+Count when we write the memory location.
 .TP
 .BR HW_BREAKPOINT_RW
-count when we read or write the memory location
+Count when we read or write the memory location.
 .TP
 .BR HW_BREAKPOINT_X
-count when we execute code at the memory location
+Count when we execute code at the memory location.
 .LP
 The values can be combined via a bitwise or, but the
 combination of
@@ -1183,7 +1183,7 @@ Time the event was active.
 Time the event was running.
 .TP
 .I cap_usr_time
-User time capability
+User time capability.
 .TP
 .I cap_usr_rdpmc
 If the hardware supports user-space read of performance counters
@@ -1577,22 +1577,22 @@ structures which each include the fields:
 .RS
 .TP
 .I from
-indicating the source instruction (may not be a branch)
+This indicates the source instruction (may not be a branch).
 .TP
 .I to
-the branch target
+The branch target.
 .TP
 .I mispred
-the branch target was mispredicted
+The branch target was mispredicted.
 .TP
 .I predicted
-the branch target was predicted
+The branch target was predicted.
 .TP
 .IR in_tx " (Since Linux 3.11)"
-the branch was in a transactional memory transaction
+The branch was in a transactional memory transaction.
 .TP
 .IR abort " (Since Linux 3.11)"
-the branch was in an aborted transactional memory transaction.
+The branch was in an aborted transactional memory transaction.
 
 .P
 The entries are from most to least recent, so the first entry
@@ -1660,90 +1660,149 @@ If
 is enabled, then a 64 bit value is recorded that is made up of
 the following fields:
 .RS
-.TP
+.TP 4
 .I mem_op
-type of opcode, a bitwise combination of
+Type of opcode, a bitwise combination of:
+
+.PD 0
+.RS
+.TP 24
 .B PERF_MEM_OP_NA
-(not available),
+Not available
+.TP
 .B PERF_MEM_OP_LOAD
-(load instruction),
+Load instruction
+.TP
 .B PERF_MEM_OP_STORE
-(store instruction),
+Store instruction
+.TP
 .B PERF_MEM_OP_PFETCH
-(prefetch), and
+Prefetch
+.TP
 .B PERF_MEM_OP_EXEC
-(executable code).
+Executable code
+.RE
+.PD
 .TP
 .I mem_lvl
-memory hierarchy level hit or miss, a bitwise combination of
+Memory hierarchy level hit or miss, a bitwise combination of:
+
+.PD 0
+.RS
+.TP 24
 .B PERF_MEM_LVL_NA
-(not available),
+Not available
+.TP
 .B PERF_MEM_LVL_HIT
-(hit),
+Hit
+.TP
 .B PERF_MEM_LVL_MISS
-(miss),
+Miss
+.TP
 .B PERF_MEM_LVL_L1
-(level 1 cache),
+Level 1 cache
+.TP
 .B PERF_MEM_LVL_LFB
-(line fill buffer),
+Line fill buffer
+.TP
 .B PERF_MEM_LVL_L2
-(level 2 cache),
+Level 2 cache
+.TP
 .B PERF_MEM_LVL_L3
-(level 3 cache),
+Level 3 cache
+.TP
 .B PERF_MEM_LVL_LOC_RAM
-(local DRAM),
+Local DRAM
+.TP
 .B PERF_MEM_LVL_REM_RAM1
-(remote DRAM 1 hop),
+Remote DRAM 1 hop
+.TP
 .B PERF_MEM_LVL_REM_RAM2
-(remote DRAM 2 hops),
+Remote DRAM 2 hops
+.TP
 .B PERF_MEM_LVL_REM_CCE1
-(remote cache 1 hop),
+Remote cache 1 hop
+.TP
 .B PERF_MEM_LVL_REM_CCE2
-(remote cache 2 hops),
+Remote cache 2 hops
+.TP
 .B PERF_MEM_LVL_IO
-(I/O memory), and
+I/O memory
+.TP
 .B PERF_MEM_LVL_UNC
-(uncached memory).
+Uncached memory
+.RE
+.PD
 .TP
 .I mem_snoop
-snoop mode, a bitwise combination of
+Snoop mode, a bitwise combination of:
+
+.PD 0
+.RS
+.TP 24
 .B PERF_MEM_SNOOP_NA
-(not available),
+Not available
+.TP
 .B PERF_MEM_SNOOP_NONE
-(no snoop),
+No snoop
+.TP
 .B PERF_MEM_SNOOP_HIT
-(snoop hit),
+Snoop hit
+.TP
 .B PERF_MEM_SNOOP_MISS
-(snoop miss), and
+Snoop miss
+.TP
 .B PERF_MEM_SNOOP_HITM
-(snoop hit modified).
+Snoop hit modified
+.RE
+.PD
 .TP
 .I mem_lock
-lock instruction, a bitwise combination of
+Lock instruction, a bitwise combination of:
+
+.PD 0
+.RS
+.TP 24
 .B PERF_MEM_LOCK_NA
-(not available) and
+Not available
+.TP
 .B PERF_MEM_LOCK_LOCKED
-(locked transaction).
+Locked transaction
+.RE
+.PD
 .TP
 .I mem_dtlb
-tlb access hit or miss, a bitwise combination of
+TLB access hit or miss, a bitwise combination of:
+
+.PD 0
+.RS
+.TP 24
 .B PERF_MEM_TLB_NA
-(not available),
+Not available
+.TP
 .B PERF_MEM_TLB_HIT
-(hit),
+Hit
+.TP
 .B PERF_MEM_TLB_MISS
-(miss),
+Miss
+.TP
 .B PERF_MEM_TLB_L1
-(level 1 TLB),
+Level 1 TLB
+.TP
 .B PERF_MEM_TLB_L2
-(level 2 TLB),
+Level 2 TLB
+.TP
 .B PERF_MEM_TLB_WK
-(hardware walker), and
+Hardware walker
+.TP
 .B PERF_MEM_TLB_OS
-(OS fault handler).
+OS fault handler
+.RE
+.PD
 .RE
 .RE
 .RE
+.IP
 .TP
 .I misc
 The
@@ -1957,15 +2016,17 @@ Files in
 The
 .I perf_event_paranoid
 file can be set to restrict access to the performance counters.
-
-2 - only allow user-space measurements
-
-1 - (default) allow both kernel and user measurements
-
-0 - allow access to CPU-specific data but not raw tracepoint samples
-
-\-1 - no restrictions
-
+.RS
+.IP 2 4
+only allow user-space measurements.
+.IP 1
+allow both kernel and user measurements (default).
+.IP 0
+allow access to CPU-specific data but not raw tracepoint samples.
+.IP \-1
+no restrictions.
+.RE
+.IP
 The existence of the
 .I perf_event_paranoid
 file is the official method for determining if a kernel supports