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perf_event_open.2 : PERF_SAMPLE_TRANSACTION support in Linux 3.13 (fwd) 

The following patch adds descriptions of the new perf_event_open.2
PERF_SAMPLE_TRANSACTION sample type as added in Linux 3.13.

The descriptions are based on information provided by Andi Kleen,
both in the e-mail

    [PATCH 1/6] perf, core: Add generic transaction flags v5

sent to the linux-kernel list as well as an e-mail

    [PATCH] Document transaction flags in perf_event_open manpage

sent to the linux-man list.

The implementation is based heavily on the Intel Haswell
processor.  Documentation can be found at this page:
http://software.intel.com/en-us/blogs/2013/05/03/intelr-transactional-synchronization-extensions-intelr-tsx-profiling-with-linux-0
as well as in section 18.11.5.1 of volume 3 of the
Intel 64 and IA-32 Architecture Software Developer's Manual.

Also, someone with better manpage formatting skills than I have
should probably investigate why I can't get the last line of
the change to properly tab-align with the .I transaction
heading.

Cowritten-by: Andi Kleen <andi@firstfloor.org>
Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Michael Kerrisk <mtk.manpages@gmail.com>
This commit is contained in:
Vince Weaver 2014-01-22 11:00:10 -05:00 committed by Michael Kerrisk
parent c46d3d7a3a
commit 1e04395903
1 changed files with 53 additions and 0 deletions
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53
man2/perf_event_open.2
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@ -699,6 +699,18 @@ in a fixed location, even though
it means having duplicate
.B SAMPLE_ID
values in records.
.TP
.BR PERF_SAMPLE_TRANSACTION " (Since Linux 3.13)"
Records reasons for transactional memory abort events
(for example, from Intel TSX transactional memory support).
The
.I precise_ip
setting must be larger than 0 and a transactional memory abort
event must be measured or no values will be recorded.
Also note that some perf_event measurements, such as sampled
cycle counting, may cause extraneous aborts (by causing an
interrupt during a transaction).
.RE
.TP
.IR "read_format"
@ -1679,6 +1691,7 @@ struct {
u64 dyn_size; /* if PERF_SAMPLE_STACK_USER */
u64 weight; /* if PERF_SAMPLE_WEIGHT */
u64 data_src; /* if PERF_SAMPLE_DATA_SRC */
u64 transaction;/* if PERF_SAMPLE_TRANSACTION */
};
.fi
.RS 4
@ -2016,6 +2029,46 @@ OS fault handler
.RE
.PD
.RE
.TP
.I transaction
If the
.B PERF_SAMPLE_TRANSACTION
flag is set then a 64-bit field is recorded describing
the sources of any transactional memory aborts.
The field is a bitwise combination of the following values:
.RS
.TP
.B PERF_TXN_ELISION
abort from an elision type transaction (Intel CPU specific)
.TP
.B PERF_TXN_TRANSACTION
abort from a generic transaction
.TP
.B PERF_TXN_SYNC
synchronous abort (related to the reported instruction)
.TP
.B PERF_TXN_ASYNC
asynchronous abort (not related to the reported instruction)
.TP
.B PERF_TXN_RETRY
retryable abort (retrying the transaction may have succeeded)
.TP
.B PERF_TXN_CONFLICT
abort due to memory conflicts with other threads
.TP
.B PERF_TXN_CAPACITY_WRITE
abort due to write capacity overflow
.TP
.B PERF_TXN_CAPACITY_READ
abort due to read capacity overflow
.RE
In addition a user-specified abort code can be obtained from
the high 32-bits of the field by shifting right by
.B PERF_TXN_ABORT_SHIFT
and masking with
.BR PERF_TXN_ABORT_MASK .
.RE
.RE
.RE