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.\" Copyright (c) 2009 Intel Corporation, Author Andi Kleen
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2009-03-30 19:33:25 +00:00
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.\" Some sentences copied from comments in arch/x86/kernel/msr.c
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.\"
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.\" Permission is granted to make and distribute verbatim copies of this
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.\" permission notice identical to this one.
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.TH MSR 4 2009-03-31 "Linux" "Linux Programmer's Manual"
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.SH NAME
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msr \- x86 CPU MSR access device
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.SH DESCRIPTION
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.I /dev/cpu/CPUNUM/msr
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provides an interface to read and write the model-specific
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registers (MSRs) of an x86 CPU.
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.I CPUNUM
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is the number of the CPU to access as listed in
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.IR /proc/cpuinfo .
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The register access is done by opening the file and seeking
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to the MSR number as offset in the file, and then
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reading or writing in chunks of 8 bytes.
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An I/O transfer of more than 8 bytes means multiple reads or writes
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of the same register.
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This file is protected so that it can only be read and written by the user
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.IR root ,
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or members of the group
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.IR root .
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.SH NOTES
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The
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.I msr
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driver is not auto-loaded.
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On modular kernels you might need to use the following command
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to load it explicitly before use:
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$ \fImodprobe msr\fP
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.SH SEE ALSO
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Intel Corporation Intel 64 and IA-32 Architectures
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arch_prctl.2, fcntl.2, flock.2, get_robust_list.2, getpriority.2, ioprio_set.2, migrate_pages.2, mmap.2, mremap.2, msync.2, sched_get_priority_max.2, sched_rr_get_interval.2, sched_setparam.2, sched_setscheduler.2, sched_yield.2, select.2, socket.2, subpage_prot.2, unshare.2, btree.3, dbopen.3, dl_iterate_phdr.3, dlopen.3, getnameinfo.3, hash.3, lockf.3, netlink.3, recno.3, rpc.3, xdr.3, cciss.4, console_ioctl.4, hpsa.4, initrd.4, msr.4, rtc.4, st.4, hosts.5, services.5, tzfile.5, aio.7, arp.7, capabilities.7, cpuset.7, feature_test_macros.7, futex.7, inotify.7, ip.7, ipv6.7, iso_8859-16.7, iso_8859-2.7, koi8-r.7, math_error.7, netlink.7, packet.7, pthreads.7, raw.7, spufs.7, udplite.7, uri.7, x25.7: Global fix: Various consistency fixes for SEE ALSO
Coauthored-by: Michael Kerrisk <mtk.manpages@gmail.com>
Signed-off-by: Michael Kerrisk <mtk.manpages@gmail.com>
2012-09-24 07:53:22 +00:00
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Software Developer's Manual Volume 3B Appendix B,
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for an overview of the Intel CPU MSRs.
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