mirror of https://github.com/tLDP/LDP
481 lines
22 KiB
Plaintext
481 lines
22 KiB
Plaintext
<!doctype linuxdoc system>
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<article>
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<title>Brief Introduction to Alpha Systems and Processors</title>
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<author>
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Neal Crook, Digital Equipment
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(Editor: <url url="mailto:davidm@azstarnet.com" name="David Mosberger">)
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</author>
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<date>V0.11, 6 June 1997
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<abstract>
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This document is a brief overview of existing Alpha CPUs, chipsets and
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systems. It has something of a hardware bias, reflecting my own area
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of expertese. Although I am an employee of Digital Equipment
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Corporation, this is not an official statement by Digital and any
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opinions expressed are mine and not Digital's.
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</abstract>
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<toc>
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<sect>What is Alpha
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<p> "Alpha" is the name given to Digital's 64-bit RISC architecture. The Alpha
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project in Digital began in mid-1989, with the goal of providing a
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high-performance migration path for VAX customers. This was not the first RISC
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architecture to be produced by Digital, but it was the first to reach the
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market. When Digital announced Alpha, in March 1992, it made the decision to
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enter the merchant semicondutor market by selling Alpha microprocessors.
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<p> Alpha is also sometimes referred to as Alpha AXP, for obscure and
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arcane reasons that aren't worth persuing. Suffice it to say that they are one
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and the same.
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<sect>What is Digital Semiconductor
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<p> <url url="http://www.digital.com/info/semiconductor/"
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name="Digital Semiconductor"> (DS) is the business unit within Digital
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Equipment Corporation (Digital - we don't like the name DEC) that
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sells semiconductors on the merchant market. Digital's products
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include CPUs, support chipsets, PCI-PCI bridges and PCI peripheral
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chips for comms and multimedia.
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<sect>Alpha CPUs
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<p>There are currently 2 generations of CPU core that implement the Alpha
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architecture:
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<itemize>
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<item> EV4
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<item> EV5
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</itemize>
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<p>Opinions differ as to what "EV" stands for (Editor's note: the true
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answer is of course "Electro Vlassic" <ref id="ref1" name="[1]">), but the
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number represents the first generation of Digital's CMOS technology
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that the core was implemented in. So, the EV4 was originally
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implemented in CMOS4. As time goes by, a CPU tends to get a mid-life
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performance kick by being optically shrunk into the next generation of
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CMOS process. EV45, then, is the EV4 core implemented in CMOS5
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process. There is a big difference between shrinking a design into a
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particular technology and implementing it from scratch in that
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technology (but I don't want to go into that now). There are a few
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other wildcards in here: there is also a CMOS4S (optical shrink in
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CMOS4) and a CMOS5L.
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<p>True technophiles will be interested to know that CMOS4 is a 0.75 micron
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process, CMOS5 is a 0.5 micron process and CMOS6 is a 0.35 micron process.
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<p>To map these CPU cores to <em/chips/ we get:
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<descrip>
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<tag/21064-150,166/ EV4 (originally), EV4S (now)
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<tag/21064-200/ EV4S
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<tag/21064A-233,275,300/ EV45
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<tag/21066/ LCA4S (EV4 core, with EV4 FPU)
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<tag/21066A-233/ LCA45 (EV4 core, but with EV45 FPU)
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<tag/21164-233,300,333/ EV5
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<tag/21164A-417/ EV56
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<tag/21264/ <url name="EV6" url="http://www.mdronline.com/report/articles/21264/21264.html">
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</descrip>
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<p> The EV4 core is a dual-issue (it can issue 2 instructions per CPU
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clock) superpipelined core with integer unit, floating point unit and
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branch prediction. It is fully bypassed and has 64-bit internal data
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paths and tightly coupled 8Kbyte caches, one each for Instruction and
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Data. The caches are write-through (they never get dirty).
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<p> The EV45 core has a couple of tweaks to the EV4 core: it has a
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slightly improved floating point unit, and 16KB caches, one each for
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Instruction and Data (it also has cache parity). (Editor's note: Neal
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Crook indicated in a separate mail that the changes to the floating
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point unit (FPU) improve the performance of the divider. The EV4 FPU
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divider takes 34 cycles for a single-precision divide and 63 cycles
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for a double-precision divide (non data-dependent). In constrast, the
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EV45 divider takes typically 19 cycles (34 cycles max) for
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single-precision and typically 29 cycles (63 cycles max) for a
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double-precision division (data-dependent).)
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<p> The EV5 core is a quad-issue core, also superpipelined, fully bypassed
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etc etc. It has tightly-coupled 8Kbyte caches, one each for I and D. These
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caches are write-through. It also has a tightly-coupled 96Kbyte on-chip
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second-level cache (the Scache) which is 3-way set associative and write-back
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(it can be dirty). The EV4->EV5 performance increase is better than just
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the increase achieved by clock speed improvements. As well as the bigger
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caches and quad issue, there are microarchitectural improvements to reduce
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producer/consumer latencies in some paths.
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<p> The EV56 core is fundamentally the same microarchitecture as the
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EV5, but it adds some new instructions for 8 and 16-bit loads and
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stores (see Section <ref id="byte ld/st" name="Bytes and all that
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stuff">). These are primarily intended for use by device drivers. The
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EV56 core is implemented in CMOS6, which is a 2.0V process.
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<p> The 21064 was anounced in March 1992. It uses the EV4 core, with a 128-bit
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bus interface. The bus interface supports the 'easy' connection of an external
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second-level cache, with a block size of 256-bits (2 data beats on the
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bus). The Bcache timing is completely software configurable. The 21064 can also
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be configured to use a 64-bit external bus, (but I'm not sure if any shipping
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system uses this mode). The 21064 does not impose any policy on the Bcache, but
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it is usually configured as a write-back cache. The 21064 does contain hooks to
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allow external hardware to maintain cache coherence with the Bcache and
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internal caches, but this is hairy.
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<p> The 21066 uses the EV4 core and integrates a memory controller and
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PCI host bridge. To save pins, the memory controller has a 64-bit data
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bus (but the internal caches have a block size of 256 bits, just like
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the 21064, therefore a block fill takes 4 beats on the bus). The
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memory controller supports an external Bcache and external DRAMs. The
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timing of the Bcache and DRAMs is completely software configurable,
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and can be controlled to the resolution of the CPU clock
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period. Having a 4-beat process to fill a cache block isn't as bad as
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it sounds because the DRAM access is done in page mode. Unfortunately,
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the memory controller doesn't support any of the new esoteric DRAMs
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(SDRAM, EDO or BEDO) or synchronous cache RAMs. The PCI bus interface
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is fully rev2.0 compliant and runs at upto 33MHz.
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<p> The 21164 has a 128-bit data bus and supports split reads, with
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upto 2 reads outstanding at any time (this allows 100% data bus
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utilisation under best-case dream-on conditions, i.e., you can
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theoretically transfer 128-bits of data on every bus clock). The 21164
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supports easy connection of an external 3-rd level cache (Bcache) and
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has all the hooks to allow external systems to maintain full cache
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coherence with all caches. Therefore, symmetric multiprocessor designs
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are 'easy'.
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<p> The 21164A was announced in October, 1995. It uses the EV56 core. It is
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nominally pin-compatible with the 21164, but requires split power rails; all
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of the power pins that were +3.3V power on the 21164 have now been split into
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two groups; one group provided 2.0V power to the CPU core, the other group
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supplies 3.3V to the I/O cells. Unlike older implementations, the 21164 pins
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are not 5V-tolerant. The end result of this change is that 21164 systems are,
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in general, not upgradeable to the 21164A (though note that it would be
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relatively straightforward to design a 21164A system that could also
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accommodate a 21164). The 21164A also has a couple of new pins to support
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the new 8 and 16-bit loads and stores. It also improves the 21164 support for
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using synchronus SRAMs to implement the external Bcache.
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<sect>21064 performance vs 21066 performance
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<p> The 21064 and the 21066 have the same (EV4) CPU core. If the same program
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is run on a 21064 and a 21066, at the same CPU speed, then the
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difference in performance comes only as a result of system
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Bcache/memory bandwidth. Any code thread that has a high hit-rate on
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the <em>internal</em> caches will perform the same. There are 2 big
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performance killers:
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<enum>
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<item> Code that is write-intensive. Even though the 21064 and the 21066
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have write buffers to swallow some of the delays, code that is
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write-intensive will be throttled by write bandwidth at the system
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bus. This arises because the on-chip caches are write-through.
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<item> Code that wants to treat floats as integers. The Alpha
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architecture does not allow register-register transfers from integer
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registers to floating point registers. Such a conversion has to be
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done via memory (And therefore, because the on-chip caches are
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write-through, via the Bcache). (Editor's note: it seems that both
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the EV4 and EV45 can perform the conversion through the primary data
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cache (Dcache), provided that the memory is cached already. In such a
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case, the store in the conversion sequence will update the Dcache and
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the subsequent load is, under certain circumstances, able to read the
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updated d-cache value, thus avoiding a costly roundtrip to the Bcache.
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In particular, it seems best to execute the stq/ldt or stt/ldq
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instructions back-to-back, which is somewhat counter-intuitive.)
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</enum>
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<p> If you make the same comparison between a 21064A and a 21066A, there is an
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additional factor due to the different Icache and Dcache sizes between the two
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chips.
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<p> Now, the 21164 solves both these problems: it achieve <em/much/
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higher system bus bandwidths (despite having the same number of signal
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pins - yes, I <em/know/ it's got about twice as many pins as a
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21064, but all those extra ones are power and ground! (yes, really!!))
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and it has write-back caches. The only remaining problem is the answer
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to the question "how much does it cost?"
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<p>
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<sect>A Few Notes On Clocking
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<p> All of the current Alpha CPUs use high-speed clocks, because their
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microarchitectures have been designed as so-called short-tick
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designs. None of the sytem busses have to run at horrendous speeds as
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a result though:
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<itemize>
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<item> on the 21066(A), 21064(A), 21164 the off-chip cache (Bcache)
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timing is completely programmable, to the resolution of the CPU
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clock. For example, on a 275MHz CPU, the Bcache read access time can
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be controller with a resolution of 3.6ns
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<item> on the 21066(A), the DRAM timing is completely programmable, to
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the resolution of the CPU clock (<em/not/ the PCI clock, the CPU clock).
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<item> on the 21064(A), 21164(A), the system bus frequency is a
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sub-multiple of the CPU clock frequency. Most of the 21064
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motherboards use a 33MHz system bus clock.
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<item> Systems that use the 21066 can run the PCI at any frequency
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relative to the CPU. Generally, the PCI runs at 33MHz.
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<item> Systems that use the APECs chipset (see Section <ref id="The
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chip-sets">) always have their CPU system bus equal to their PCI bus
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frequency. This means that both busses tends to run at either 25MHz or
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33MHz (since these are the frequencies that scale up to match the CPU
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frequencies). On APECs systems, the DRAM controller timings are
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software programmable in terms of the CPU system bus frequency
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</itemize>
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<bf/Aside:/ someone suggested that they were getting bad performance
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on a 21066 because the 21066 memory controller was only running at
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33MHz. Actually, it's the superfast 21064A systems that have memory
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controllers that 'only' run at 33MHz.
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<sect>The chip-sets <label id="The chip-sets">
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<p> DS sells two CPU support chipsets. The 2107x chipset (aka APECS) is a
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21064(A) support chiset. The 2117x chipset (aka ALCOR) is a 21164 support
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chipset. There will also be 2117xA chipset (aka ALCOR 2) as a 21164A support
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chipset.
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<p> Both chipsets provide memory controllers and PCI host bridges for their
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CPU. APECS provides a 32-bit PCI host bridge, ALCOR provides a 64-bit PCI host
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bridge which (in accordance with the requirements of the PCI spec) can support
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both 32-bit and 64-bit PCI devices.
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<p>
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APECS consists of 6, 208-pin chips (4, 32-bit data slices (DECADE), 1
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system controller (COMANCHE), 1 PCI controller (EPIC)). It provides a DRAM
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controller (128-bit memory bus) and a PCI interface. It also does all the work
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to maintain memory coherence when a PCI device DMAs into (or out of) memory.
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<p> ALCOR consists of 5 chips (4, 64-bit data slices (Data Switch, DSW) -
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208-pin PQFP and 1 control (Control, I/O Address, CIA) - a 383 pin plastic PGA).
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It provides a DRAM controller (256-bit memory bus) and a PCI interface. It
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also does all the work required to support an external Bcache and to
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maintain memory coherence when a PCI device DMAs into (or out of) memory.
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<p> There is no support chipset for the 21066, since the memory controller and
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PCI host bridge functionality are integrated onto the chip.
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<sect>The Systems
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<p> The applications engineering group in DS produces example designs using the
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CPUs and support chipsets. These are typically PC-AT size motherboards, with
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all the functionality that you'd typically find on a high-end Pentium
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motherboard. Originally, these example designs were intended to be used as
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starting points for third-parties to produce motherboard designs from. These
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first-generation designs were called Evaluation Boards (EBs). As the
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amount of engineering required to build a motherboard has increased (due to
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higher-speed clocks and the need to meet RF emission and susceptibility
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regulations) the emphasis has shifted towards providing motherboards that
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are suitable for volume manufacture.
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<p> Digital's system groups have produced several generations of machines using
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Alpha processors. Some of these systems use support logic that is designed by
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the systems groups, and some use commodity chipsets from DS. In some cases,
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systems use a combination of both.
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<p> Various third-parties build systems using Alpha processors. Some of these
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companies design systems from scratch, and others use DS support chipsets,
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clone/modify DS example designs or simply package systems using build and
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tested boards from DS.
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<p> The EB64: Obsolete design using 21064 with memory controller implemented
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using programmable logic. I/O provided by using programmable logic to interface
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a 486<->ISA bridge chip. On-board Ethernet, SuperI/O (2S, 1P, FD), Ethernet
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and ISA. PC-AT size. Runs from standard PC power supply.
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<p> The EB64+: Uses 21064 or 21064A and APECs. Has ISA and PCI expansion (3
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ISA, 2 PCI, one pair are on a shared slot). Supports 36-bit DRAM SIMs. ISA bus
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generated by Intel SaturnI/O PCI-ISA bridge. On-board SCSI (NCR 810 on PCI)
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Ethernet (Digital 21040), KBD, MOUSE (PS2 style), SuperI/O (2S, 1P, FD),
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RTC/NVRAM. Boot
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ROM is EPROM. PC-AT size. Runs from standard PC power supply.
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<p> The EB66: Uses 21066 or 21066A. I/O sub-system is identical to EB64+. Baby
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PC-AT size. Runs from standard PC power supply. The EB66 schematic was
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published as a marketing poster advertising the 21066 as "the first
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microprocessor in the world with embedded PCI" (for trivia fans: there are
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actually 2 versions of this poster - I drew the circuits and wrote the spiel
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for the first version, and some Americans mauled the spiel for the second
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version)
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<p> The EB164: Uses 21164 and ALCOR. Has ISA and PCI expansion (3 ISA slots,
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2 64-bit PCI slots (one is shared with an ISA slot) and 2 32-bit PCI slots.
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Uses plus-in Bcache SIMMs. I/O sub-system provides SuperI/O (2S, 1P, FD),
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KBD, MOUSE (PS2 style), RTC/NVRAM. Boot ROM is Flash. PC-AT-sized motherboard.
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Requires power supply with 3.3V output.
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<p> The AlphaPC64 (aka Cabriolet): derived from EB64+ but now baby-AT
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with Flash boot ROM, no on-board SCSI or Ethernet. 3 ISA slots, 4 PCI
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slots (one pair are on a shared slot), uses plug-in Bcache SIMMs.
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Requires power supply with 3.3V output.
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<p> The AXPpci33 (aka NoName), is based on the EB66. This design is produced by
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Digital's Technical OEM (TOEM) group. It uses the 21066 processor running at
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166MHz or 233MHz. It is a baby-AT size, and runs from a standard PC power
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supply. It has 5 ISA slots and 3 PCI slots (one pair are a shared slot). There
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are 2 versions, with either PS/2 or large DIN connectors for the keyboard.
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<p> Other 21066-based motherboards: most if not all other 21066-based
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motherboards on the market are also based on EB66 - there's really not many
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system options when designing a 21066 system, because all the control is done
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on-chip.
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<p> Multia (aka the Universal Desktop Box): This is a very compact
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pedestal desktop system based on the 21066. It includes 2 PCMCIA
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sockets, 21030 (TGA) graphics, 21040 Ethernet and NCR 810 SCSI disk
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along with floppy, 2 serial ports and a parallel port. It has limited
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expansion capability (one PCI slot) due to its compact size. (There is
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some restriction on when you can use the PCI slot, can't remember
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what) (Note that 21066A-based and Pentium-based Multia's are also
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available).
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<p> DEC PC 150 AXP (aka Jensen): This is a very old Digital system - one of the
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first-generation Alpha systems. It is only mentioned here because a number of
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these systems seem to be available on the second-hand market. The Jensen is a
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floor-standing tower system which used a 150MHz 21064 (later versions used
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faster CPUs but I'm not sure what speeds). It used programmable logic to
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interface a 486 EISA I/O bridge to the CPU.
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<p> Other 21064(A) systems: There are 3 or 4 motherboard designs around (I'm
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not including Digital <em>systems</em> here) and all the ones I know of
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are derived from the EB64+ design. These include:
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<itemize>
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<item>EB64+ (some vendors package the board and sell it unmodified); AT
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form-factor.
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<item>Aspen Systems motherboard: EB64+ derivative; baby-AT form-factor.
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<item>Aspen Systems server board: many PCI slots (includes PCI bridge).
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<item>AlphaPC64 (aka Cabriolet), baby AT form-factor.
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</itemize>
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<p> Other 21164(A) systems: The only one I'm aware of that isn't simply
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an EB164 clone is a system made by DeskStation. That system is implemented
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using a memory and I/O controller proprietary to Desk Station. I don't know
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what their attitude towards Linux is.
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<sect>Bytes and all that stuff<label id="byte ld/st">
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<p> When the Alpha architecture was introduced, it was unique amongst RISC
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architectures for eschewing 8-bit and 16-bit loads and stores. It supported
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32-bit and 64-bit loads and stores (longword and quadword, in Digital's
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nomenclature). The co-architects (Dick Sites, Rich Witek) justified this
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decision by citing the advantages:
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<enum>
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<item> Byte support in the cache and memory
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sub-system tends to slow down accesses for 32-bit and 64-bit quantities.
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<item> Byte support makes it hard to build high-speed error-correction
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circuitry into the cache/memory sub-system.
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</enum>
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<p> Alpha compensates by providing powerful instructions for
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manipulating bytes and byte groups within 64-bit registers. Standard
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benchmarks for string operations (e.g., some of the Byte benchmarks) show
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that Alpha performs very well on byte manipulation.
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<p> The absence of byte loads and stores impacts some software semaphores and
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impacts the design of I/O sub-systems. Digital's solution to the I/O problem is
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to use some low-order address lines to specify the data size during I/O
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transfers, and to decode these as byte enables. This so-called Sparse
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Addressing wastes address space and has the consequence that I/O space is
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non-contiguous (more on the intricacies of Sparse Addressing when I get around
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to writing it). Note that I/O space, in this context, refers to all system
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resources present on the PCI and therefore includes both PCI memory space and
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PCI I/O space.
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<p> With the 21164A introduction, the Alpha archtecture was ECO'd to include
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byte addressing. Executing these new instructions on an earlier CPU will cause
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an OPCDEC PALcode exception, so that the PALcode will handle the access. This
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will have a performance impact. The ramifications of this are that use of these
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new instructions (IMO) should be restricted to device drivers rather than
|
|
applications code.
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|
|
|
<p> These new byte load and stores mean that future support chipsets will be
|
|
able to support contiguous I/O space.
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|
|
|
|
|
<sect> PALcode and all that stuff
|
|
|
|
<p> This is a placeholder for a section explaining PALcode. I will write it if
|
|
there is sufficient interest.
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|
|
|
<sect>Porting
|
|
|
|
<p> The ability of any Alpha-based machine to run Linux is really only limited
|
|
by your ability to get information on the gory details of its innards. Since
|
|
there are Linux ports for the E66, EB64+ and EB164 boards, all systems based on
|
|
the 21066, 21064/APECS or 21164/ALCOR should run Linux with little or no
|
|
modification. The major thing that is different between any of these
|
|
motherboards is the way that they route interrupts. There are three sources of
|
|
interrupts:
|
|
|
|
<itemize>
|
|
<item> on-board devices
|
|
<item> PCI devices
|
|
<item> ISA devices
|
|
</itemize>
|
|
|
|
<p> All the systems use an Intel System I/O bridge (SIO) to act as a
|
|
bridge between PCI and ISA (the main I/O bus is PCI, the ISA bus is a
|
|
secondary bus used to support slow-speed and 'legacy' I/O
|
|
devices). The SIO contains the traditional pair of daisy-chained
|
|
8259s.
|
|
|
|
<p> Some systems (e.g., the Noname) route all of their interrupts
|
|
through the SIO and thence to the CPU. Some systems have a separate
|
|
interrupt controller and route all PCI interrupts plus the SIO
|
|
interrupt (8259 output) through that, and all ISA interrupts through
|
|
the SIO.
|
|
|
|
<p> Other differences between the systems include:
|
|
|
|
<itemize>
|
|
<item> how many slots they have
|
|
<item> what on-board PCI devices they have
|
|
<item> whether they have Flash or EPROM
|
|
</itemize>
|
|
|
|
<sect>More Information
|
|
|
|
<p> All of the DS evaluation boards and motherboard designs are
|
|
license-free and the whole documentation kit for a design costs about
|
|
\$50. That includes all the schematics, programmable parts sources,
|
|
data sheets for CPU and support chipset. The doc kits are available
|
|
from Digital Semiconductor distributors. I'm not suggesting that many
|
|
people will want to rush out and buy this, but I do want to point out
|
|
that the information is available.
|
|
|
|
|
|
<p>Hope that was helpful. Comments/updates/suggestions for expansion
|
|
to <url url="mailto:neal.crook@reo.mts.digital.com" name="Neal Crook">.
|
|
|
|
<sect>References
|
|
|
|
<p><label id="ref1"><url url="http://www.research.digital.com/wrl/publications/abstracts/TN-13.html" name="[1]">
|
|
Bill Hamburgen, Jeff Mogul, Brian Reid, Alan Eustace, Richard Swan,
|
|
Mary Jo Doherty, and Joel Bartlett. <em>Characterization of Organic
|
|
Illumination Systems</em>. DEC WRL, Technical Note 13, April 1989.
|
|
|
|
</article>
|